F105 Search Results

application of parity checker/generator

Abstract: PQO-10 F10170 F10570
Contextual Info: F1017Ö« F10570 11-INPUT PARITY CHECKER/GENERATOR D E S C R IP T IO N — T h e F 1 0 1 70 a n d F1 0 5 70 a re v e ry h ig h -s p e e d 1 1 -In p u t P a rity C h e c k ­ e r /G e n e ra to rs . It is u s e fu l f o r d a ta p ro c e s s in g , m e m o ry a n d d a ta tr a n s m is s io n a p p lic a ­

F10166

Abstract: F10566
Contextual Info: F10166^ F10566 5-BIT COMPARATOR F10K VOLTAGE COMPENSATED ECL DESCRIPTION - The F10166/F10566 are high-speed expandable 5-Bit Comparators for comparing the magnitude of two binary words. Two outputs are provided: A>B and A<B. A = B can be obtained by NORing the two outputs with an additional gate. A HIGH level on the

F10132

Abstract: F10532
Contextual Info: F10132 • F10532 DUAL MULTIPLEXER/LATCH h QnnaratoT h F1° 132 and F10532 are dual m ultiplexers w ith D type latches !? S° lect and Reset i nP“ ts. Each latch may be enabled “ LOGIC SYMBOL In a b « f p 'u n n i fl*K ^ 0n Enable <Ec) in ,he LOW sta,e or bV using the

F10186

Abstract: F10586 low power T Flip-Flop
Contextual Info: I HEX D FLIP-FLOP WITH RESET F10K VOLTAGE COMPENSATED ECL D E S C R I P T I O N — T h e F10186 and F10586 co n ta in six h ig h -sp e e d m aster/slave D -type flip -flo p s w h ich have a c o m m o n c lo c k . D ata is entered into th e m aster w hen th e C lo c k is

F10162

Abstract: F10562 decoder active high outputs
Contextual Info: F10162 • F10562 l-OF-8 DECODER ACTIVE HIGH OUTPUTS D E S C R IP TIO N — T h e F10162 a n d F10562 a c c e p t a 3 -b it b in a r y in p u t a n d p ro v id e s e ig h t m u tu a lly e x c lu s iv e o u tp u ts . T h e s e le c te d o u tp u t w ill be H IG H w h ile a ll o th e r

F10135

Abstract: F10535 fairchild ECL
Contextual Info: F10135~* F 1 0 5 3 5 ^ F10K VOLTAGE COMPENSATED ECL DUAL JK FLIP-FLOP DESCRIPTION - The F10135 and F10535 are Dual Master/Slave DC Coupled Flip­ Flop. Asynchronous Clear Direct CD and Set Direct (SD) are provided and override the clock. The output states of each flip-flop change on the LOW to HIGH transition of

F10141

Abstract: F10541
Contextual Info: F10141 • F10541 UNIVERSAL SHIFT REGISTER F10K VOLTAGE COMPENSATED ECL DESCRIPTION - The F1Q141/F10541 contains four clocked D type flip-flops with individual inputs and outputs for parallel operations, and with serial inputs and steering logic for bidirectional shifting. T he flip-flops accept input data a set-up tim e before the positive-going

bcd counter using j-k flip flop diagram

Abstract: pn sequence generator using jk flip flop F10136 ECL Handbook
Contextual Info: / / / F10136 • F10536 • F10137 • F10537 V 4-STAGE UP/DOWN COUNTERS F10K VOLTAGE COMPENSATED ECL DESCRIPTION - The F10136/F10536 and F10137/FI 0537 are 4-stage synchronous counters capable of operating at typical count rates of 250 MHz. The circuits are designed

Contextual Info: F10176^ F10576^ HIGH SPEED HEX D FLIP-FLOP F10K VOLTAGE COMPENSATED ECL D E S C R IP TIO N — The F10176 and F10576 contain six high-speed master/slave D type flip-flops which have a common Clock. Data is entered into the master when the Clock is LOW. Data transfer takes place on the positive-going clock transition. A change in the

8 bit adder and subtractor

Abstract: F10580 ECL ADDER adder H1211 F10180
Contextual Info: ; F10180 • F10580 / F10K VOLTAGE COMPENSATED ECL DUAL 2-BIT ADDER/SUBTRACTOR DESCRIPTION - The F10180/F10580 are high-speed, low-power Dual 2-Bit Adder/ Subtractors. It is designed to be used in special purpose adder/subtractors or in high speed multiplier arrays. Inputs for each adder are Carry-in, Operand A, and Operand B;

12J2

Abstract: 1.2j2 F10535 F10135
Contextual Info: F10135^ F10535 F10K VOLTAGE COMPENSATED ECL DUAL JK FLIP-FLOP DESCRIPTION - The F10135 and F10535 are Dual Master/Slave DC Coupled FlipFlop. Asynchronous Clear Direct CD and Set Direct (SD) are provided and override the clock. The output states of each flip-flop change on the LOW to HIGH transition of

F1057

Contextual Info: F10175 • F10575 QUINT LATCH DESCRIPTION — The F10175 and F10575 are high-speed low-power Quint Latches. They feature five D type latches with common Reset and a common 2-input Enable. Data is transferred on the negative edge of the enable and latched on the positive edge.

Contextual Info: F1017Ó7* F10570 11-INPUT PARITY CHECKER/GENERATOR D E S C R IP TIO N — The F10170 and F10570 are very high-speed 11-In p u t Parity C heck­ er/G ene rato rs. It is useful fo r data processing, m e m ory and data tra nsm ission a p p lic a ­ tio n s. T w o o u tp u ts are provided; PoO-8 is H IG H w hen the re is an odd n u m b e ro f H IG H

F10116

Contextual Info: F10115 • F10116 • F10515 • F10516 LINE RECEIVERS DESCRIPTION — The F10115 and F10116 are d iffe re n tia l am p lifiers w ith low im­ pedance em itter-follow er outputs. An internal reference supply V b b is available for added ve rsatility. Active current sources provide im proved comm on mode rejection.

Contextual Info: F10153 • F10553 FIOK VOLTAGE COMPENSATED ECL QUAD D LATCH DESCRIPTION - The F10153/F10553 are high-speed Quad D Latches consisting of four bistable latch circuits with D type inputs and gated Q outputs. The gated outputs allow direct wiring to a bus. When the enable is LOW, outputs will follow the D inputs.

Contextual Info: Laser Diodes T-Series 976nm Wavelength locked High Power Laser Diode Module M976±0.5-35-F105/22-T4S Features: Narrow line width<0.5nm 976nm wavelength locked Output Power: 35W 105 m core 0.22NA multimode optical fiber Fiber laser feedback protection Electrically isolated housing

Contextual Info: F10135 • F10535 F10K VOLTAGE COMPENSATED ECL DUAL JK FLIP-FLOP DESCRIPTION - The F10135 and F10535 are Dual Master/Slave DC Coupled FlipFlop. Asynchronous Clear Direct CD and Set Direct (SD) are provided and override the clock. The output states of each flip-flop change on the LOW to HIGH transition of

the pin function of ic 7107

Abstract: F10581 7108f
Contextual Info: F10181 • F10581 4-BIT ALU/FUNCTION GENERATOR F10K VOLTAGE COMPENSATED ECL DESCRIPTION — The F10181 and F10581 are high-speed arithm etic logic units capa­ ble of performing 16 logic operations and 16 arithm etic operations on two 4-bit words. Full internal carry is incorporated for ripple through operation.

Contextual Info: F10145A • F10545A 16 x 4 REGISTER FILE RAM F1QK-VOLTAGE COMPENSATED ECL GENERAL DESCRIPTION - The F10145A and F10545A are high-speed 64-bit Random Access Memories organized as a 16-word by 4-bit array. External logic requirements are minimized by internal address decoding, while memory expansion and data bussing are

Contextual Info: HEX D FLIP-FLOP WITH RESET F10K VOLTAGE COMPENSATED ECL D E S C R IP T IO N — T h e F 1 0 186 an d F10586 contain six h igh -sp e e d m aster/slave D -typ e flip -flo ps w h ich have a co m m o n clock. D ata is entered into the m aster w hen the C lo c k is

si117

Contextual Info: F10136 • F10536 • F10137 • F10537 4-STAGE UP/DOWN COUNTERS F10K VOLTAGE COMPENSATED ECL DESCRIPTION - The F10136/F10536 and F10137/F10537 are 4-stage synchronous counters capable of operating at typical count rates ot 250 MHz. The circuits are designed

F10161

Contextual Info: F10161 • F10561 l-OF-8 DECODER ACTIVE LOW OUTPUTS DESCRIPTION — The F10161 and F10561 accept a 3-bit binary input and provides eight m utually exclusive outputs. The selected output w ill be LOW while all other outputs are HIGH. Two enable inputs force all outputs HIGH when either or both are

Contextual Info: polyfet rf devices F1058 PATENTED GOLD METALIZED General Description Silicon DMOS designed specifically for RF applications. Immune to forward and reverse bias secondary breakdown "Polyfet"1“1 process features gold metal for greatly extended lifetime. Low output capacitance

Contextual Info: F10160 • F10560 12-BIT PARITY CHECKER/GENERATOR DESCRIPTION — The F10160 and F10560 are 12-Input Parity Generators. The output w ill be HIGH when an odd number of inputs are HIGH; typical delay is 4 ns. For applications requiring fewer than 12 inputs, unused inputs may be left open, since