FCS SDLC Search Results

SCN26562C4A52

Contextual Info: Philips Semiconductors Product specification Dual universal serial communications controller DUSCC DESCRIPTION SCN26562 • Parity and FCS (frame check sequence LRC or CRC) generation and checking The Philips Semiconductors SCN26562 Dual Universal Serial

intel 8273

Abstract: interfacing of 8257 with 8086 8086 8257 DMA controller interfacing interfacing of 8257 devices with 8085 8273 dma controller GA27-3093 8273 disk controller 8086 8257 DMA controller 8257 DMA controller intel 8257 interrupt controller
Contextual Info: in te i 8273 PROGRAMMABLE HDLC/SDLC PROTOCOL CONTROLLER CCITT X.25 Compatible HDLC/SDLC Compatible Full Duplex, Half Duplex, or Loop SDLC Operation Up to 64K Baud Synchronous Transfers Automatic FCS CRC Generation and Checking Up to 9.6K Baud with On-Board Phase

rdn 100

Abstract: SCN26562 SCN26562C4A52 SCN26562C4N48
Contextual Info: Philips Semiconductors Product specification Dual universal serial communications controller DUSCC SCN26562 • Parity and FCS (frame check sequence LRC or CRC) generation DESCRIPTION The Philips Semiconductors SCN26562 Dual Universal Serial Communications Controller (DUSCC) is a single-chip MOS-LSI

Intel 8080 CPU Diagram

Abstract: intel 8273 IBM 8080 Intel 8080 block Diagram intel 8085 a hdlc sdlc chip intel 8080 architecture intel 8085 MCS intel 8080 MCS intel 8085 clock
Contextual Info: in le l 8273 PROGRAMMABLE HDLC/SDLC PROTOCOL CONTROLLER CCITT X.25 Compatible Programmable NRZI Encode/Decode HDLC/SDLC Compatible Two Programmable Modem Control Ports Full Duplex, Half Duplex, or Loop SDLC Operation Up to 64K Baud Synchronous Transfers Automatic FCS CRC Generation and

receiver philips fr 310

Abstract: RIA 250
Contextual Info: Philips Semiconductors Data Communications Products Product specification Dual universal serial communications controller DUSCC DESCRIPTION SCN26562 • Parity and FCS (fram e check sequence LR C or CRC) generation The Philips Sem iconductors SC N26562 Dual Universal Serial

VL1935-13PC

Contextual Info: V L S I Tech nology , in c . VL1935 SYNCHRONOUS DATA LINE CONTROLLER FEATURES • HDLC, SDLC, ADCCP and CCITT X.25 Compatible • Global Address Recognition • SDLC Loop Data Link Capability • Extendable Control Field • Full or Half Duplex Operation • Automatic Zero Insertion and Deletion

hdlc

Abstract: LC4256ZE 4000ZE CRC-16 CRC-32 VHDL CODE FOR HDLC controller ispLEVER iso
Contextual Info: HDLC Controller Implemented in ispMACH 4000ZE and CPLD Families July 2009 Reference Design RD1009 Introduction High-Level Data Link Control HDLC is published by the International Standards Organization (ISO). This data link protocol is located at the link layer (layer 2) of the 7-layer OSI reference model. Today, a variety of link layer protocols such as LAPB, LAPD, LLC and SDLC are based on the HDLC protocol with a few modifications. These singlechannel and multi-channel HDLC controller reference designs, targeted for the ispMACH 4000ZE, 4000 and

p03 smd

Abstract: SMD A7H IA8X44-PDW40I-R-P03 P8044AH RBL 43 P TP8044AH intel 8044 p8044 P8344AH SMD B8H
Contextual Info: IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER 28 August 2007 As of Production Version P03 IA8044/IA8344 SDLC Communications Controller Data Sheet Copyright 2007 IA211010112-02 © Page 1 of 48 www.Innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344

Contextual Info: IA8044/IA8344 Data Sheet SDLC COMMUNICATIONS CONTROLLER As of Production Version 01 innovASIC FEATURES • • • • • • • • • • • • • • • • Form, Fit, and Function Compatible with the Intel 8X44 Packaging options available: 40 Pin Plastic Dual In-Line Package PDIP ,

SMD A7H

Abstract: P8344AH TN8344AH intel 8044 P8344 RBL 43 P SMD B8H p8044 SDLC 8044 smd b5h
Contextual Info: IA8044/IA8344 Data Sheet SDLC COMMUNICATIONS CONTROLLER innovASIC FEATURES • • • • • • • • • • • • • • • • Form, Fit, and Function Compatible with the Intel 8044/8344 Packaging options available: 40 Pin Plastic Dual In-Line Package PDIP ,

SMD A7H

Abstract: intel 8044 n8044ah SMD B8H ASM51 RBL 43 P p8044ahr0117 RBL43 TP8044 SMD e7H
Contextual Info: IA8044/IA8344 Data Sheet SDLC COMMUNICATIONS CONTROLLER As of Production Version P03 innovASIC FEATURES • • • • • • • • • • • • • • • • Form, Fit, and Function Compatible with the Intel 8044/8344 Packaging options available: 40 Pin Plastic Dual In-Line Package PDIP ,

RFC1662

Abstract: RFC-1662 iso 3309 SCD240110QCM CD2401 intel DMA controller scd243110qcd hdlc IN SDLC PROTOCOL CD2231
Contextual Info: product brief Intel WAN Controllers Product Highlights • Multi-protocol support: async, sync HDLC/SDLC high-level data link control/ synchronous data link control ■ On-chip 32-bit address, 16-bit data, doublebuffered DMA controller for each transmitter

GA27-3093-2

Abstract: DAL00
Contextual Info: rz 7 S C S -T H O M S O N TECHNICAL MANUAL MK5029 SDLC LINK LEVEL CONTROLLER TABLE OF CONTENTS SECTION PAGE SECTION 1 INTRODUCTION Introduction 3 SECTION 2 FEATURES Feature 3 SECTION 3 OPERATIONAL DESCRIPTION 3.1 Functional B lo c k s .

MC68B54P

Abstract: MC68B54 MC6854 MC68A54P mc6854p MC68A54 MC6854L MC68B54L MC6864 MC6854CS
Contextual Info: MOTOROLA ADVANCED DATA-LINK CONTROLLER ADLC The MC6854 ADLC performs the complex M PU /data communication link function for the "Advanced Data Communication Control Pro­ cedure" (ADCCP), High-Level Data-Link Control (HDLC) and Syn­ chronous Data-Link Control (SDLC) standards. The ADLC provides key

STK 412 770

Abstract: stk 412 -770 CL-CD2431 GT1 X02 stk 713 80X86 CL-CD2231 CL-CD2401 stk 412 240 diagram STK 4272
Contextual Info: CL-CD2431  Data Book FEATURES • Four full-duplex multi-protocol channels, each running up to 134.4 kbits/second with CLK = 35 MHz ■ Supports async, async-HDLC (high-level data link control), and HDLC/SDLC (synchronous data link control; non-multidrop) on all channels

stk 142 - 150

Abstract: STK 4272 GT1 X02 RFC-1055 BW144 80X86 CL-CD2231 CL-CD2401 CL-CD2431 stk 4242
Contextual Info: CL-CD2431 Data Book FEATURES • Four full-duplex multi-protocol channels, each running up to 134.4 kbits/second with CLK = 35 MHz ■ Supports async, async-HDLC (high-level data link control), and HDLC/SDLC (synchronous data link control; non-multidrop) on all channels

DB15 dwg

Abstract: CRC-16 DB01 DB03 SCN2653
Contextual Info: Philips Semiconductors Product specification Multi-protocol communications controller MPCC DESCRIPTION SCN2652/SCN68652 FEATURES • DC to 2Mbps data rate • Bit-oriented protocols (BOP): SDLC, ADCCP, HDLC • Byte-control protocols (BCP): DDCMP, BISYNC (external CRC)

RFC-1331

Abstract: 105GT-2 80X86 CL-CD2401 CL-CD2431 gt22a iso 3309
Contextual Info: CL-CD2430/CD2431 DataBook i "CIRRUS LOGIC FEATURES • Intelligent 4-Channel Local and WAN Communications Controller Four full-duplex multi-protocol channels, each running up to 128 kbits/second ■ Supports async, async-HDLC high-level data link control , and HDLC/SDLC (synchronous data link

intel 8044

Abstract: p8344ah TN8344AH P8344 smd marking b4h p8044 TP8044AH intel smd diode marking d3h smd code marking SP3 P8044AHR0117
Contextual Info: IA8044/IA8344 SDLC Communications Controller Data Sheet March 30, 2010 IA8044/IA8344 SDLC Communications Controller Data Sheet ® IA211010112-04 UNCONTROLLED WHEN PRINTED OR COPIED Page 1 of 65 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344

Contextual Info: in te * M8744H RUPITM-44: REMOTE UNIVERSAL PERIPHERAL INTERFACE Military M8744H-8044 with User Programmable/Erasable EPROM Fully Compatible with 8051 CPU 8-Bit CPU Plus Independent HDLC/SDLC Protocol Controller 4K x 8 EPROM, 192 x 8 RAM Boolean Processor External Memory Expandable to 128K

RBL 43 P

Contextual Info: IA8044/IA8344 SDLC Communications Controller Data Sheet March 30, 2010 IA8044/IA8344 SDLC Communications Controller Data Sheet ® IA211010112-04 UNCONTROLLED WHEN PRINTED OR COPIED Page 1 of 65 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA8044/IA8344

Contextual Info: intei M8744H RUPITM-44: REMOTE UNIVERSAL PERIPHERAL INTERFACE Military M8744H-8044 with User Programmable/Erasable EPROM Fully Compatible with 8051 CPU 8-Bit CPU Plus Independent HDLC/SDLC Protocol Controller 4K x 8 EPROM, 192 x 8 RAM Boolean Processor External Memory Expandable to 128K

JRC 45600

Abstract: YD 803 SGS 45600 JRC TDA 7277 TDA 5072 krp power source sps 6360 2904 JRC Sony SHA T90 SA philips HFE 4541
Contextual Info: I SEMICON INDEXES Contents and Introduction Manufacturers' Information V O LU M E 3 INTERNATIONAL INTEGRATED CIRCUITS INDEX 15th EDITION 1997 Numerical Listing of Integrated Circuits Substitution Guide U D C 621.382.3 Diagram s THE S E M IC O N INTERNATIONAL INDEXES

P8344AH

Abstract: N8344AH TN8344AH p8044ah TP8044AH N8044AH p8044 RUPI-44 P8044AHR0117 p8044ah-r0117
Contextual Info: IA8044/IA8344 Preliminary Data Sheet SDLC COMMUNICATIONS CONTROLLER As of Production Version 00 FEATURES • • • • • • • • • • • • • • • • Form, Fit, and Function Compatible with the Intel 8X44 Packaging options available: 40 Pin Plastic Dual In-Line Package PDIP , 44