3sk300
Abstract: DB64 DSA003642
Text: 3SK300 Silicon N Channel Dual Gate MOS FET UHF / VHF RF Amplifier ADE-208-449A Z 2nd. Edition Mar. 2001 Features • Low noise figure NF = 1.0 dB typ. at f = 200 MHz • High gain PG = 27.6 dB typ. at f = 200 MHz Outline MPAK-4 2 3 1 4 Note: Marking is “ZR–”
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3SK300
ADE-208-449A
3sk300
DB64
DSA003642
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SLG55221
Abstract: fet n-channel pin configuration FET marking code
Text: 2 Rail GreenFETTM High Voltage Gate Driver Features Pin Configuration 5V Power supply • Drain Voltage Range 1.0V to 20V • • VCC • Controlled Turn on Slew Rate • TDFN-8 Package 2 4 3 8 7 6 5 PG G1/G2 S/DIS1 D 8-pin TDFN Top View Environmental Application Functions
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SLG55221
SLG55220
SLG55221
fet n-channel pin configuration
FET marking code
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SLG55221
Abstract: FET MARKING 600 V logic level fet fet MARKING g2 fet n-channel pin configuration
Text: 2 Rail GreenFETTM High Voltage Gate Driver Features Pin Configuration 5V Power supply • Drain Voltage Range 1.0V to 20V • • VCC • Controlled Turn on Slew Rate • TDFN-8 Package 2 4 3 8 7 6 5 PG G1/G2 S/DIS1 D 8-pin TDFN Top View Environmental Application Functions
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SLG55221
SLG55220
SLG55221
FET MARKING
600 V logic level fet
fet MARKING g2
fet n-channel pin configuration
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IRF7907PBF
Abstract: No abstract text available
Text: IRF7907PbF-1 HEXFET Power MOSFET VDS 30 RDS on m ax Q1 V 16.4 (@VGS = 10V) mΩ RDS(on) m ax Q2 11.8 (@VGS = 10V) Qg (typical) Q1 6.7 Qg (typical) Q2 14 ID(@TA = 25°C)Q1 9.1 ID(@TA = 25°C)Q2 11 nC S2 1 8 D2 G2 2 7 D2 S1 3 6 D1 G1 4 5 D1 SO-8 A Applications
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IRF7907PbF-1
IRF7907PBF
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Untitled
Abstract: No abstract text available
Text: IRF7904PbF-1 HEXFET Power MOSFET VDS 30 RDS on max Q1 V 16.2 (@VGS = 10V) mΩ RDS(on) max Q2 10.8 (@VGS = 10V) Qg (typical) Q1 7.5 Qg (typical) Q2 14 ID(@TA = 25°C)Q1 7.6 ID(@TA = 25°C)Q2 11 nC G1 1 8 D1 S2 2 7 S1 / D2 S2 3 6 S1 / D2 G2 4 5 S1 / D2 SO-8
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IRF7904PbF-1
D-020D
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IRF9910PBF
Abstract: No abstract text available
Text: IRF9910PbF-1 VDS 20 RDS on m ax Q1 HEXFET Power MOSFET V 13.4 (@VGS = 10V) mΩ RDS(on) m ax Q2 9.3 (@VGS = 10V) Qg (typical) Q1 7.4 Qg (typical) Q2 15 ID(@TA = 25°C)Q1 10 nC S2 1 8 D2 G2 2 7 D2 S1 3 6 D1 G1 4 5 D1 SO-8 A ID(@TA = 25°C)Q2 12 Applications
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IRF9910PbF-1
IRF9910PBF
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NEC uPA 63 H
Abstract: NEC uPA 63 NEC uPA 63 a NEC uPA 71 GL124 MEL12 UPA672T UPA572T UPA602 nec sc-59 fet
Text: DATA SHEET MOS FIELD EFFECT TRANSISTOR ,uPA502T N-CHANNEL MOS FET 5-PIN 2 CIRCUITS The pPA502T is a mini-mold device provided with two MOS FET circuits. It achieves high-density mounting and saves mounting costs. PACKAGE DIMENSIONS (in millimeters) 0.32 +O.’
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uPA502T
pPA502T
SC-59
pPA503T
NEC uPA 63 H
NEC uPA 63
NEC uPA 63 a
NEC uPA 71
GL124
MEL12
UPA672T
UPA572T
UPA602
nec sc-59 fet
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TRANSISTOR SMD MARKING CODE s7
Abstract: marking code G7 SMD Transistor g3 smd transistor SMD Transistor G6 SMD Transistor Marking Code S7 g3 smd transistor view TRANSISTOR SMD MARKING CODE GFs fet diode date sheet FET MARKING CODE s5 smd transistor g3
Text: Philips Semiconductors Product specification N-channel enhancement mode TrenchMOS transistor array FEATURES PHN70308 SYMBOL • 30 mΩ isolation transistor • 80 mΩ spindle transistors • TrenchMOS technology • Logic level compatible • Surface mount package
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PHN70308
PHN70308
OT341
TRANSISTOR SMD MARKING CODE s7
marking code G7 SMD Transistor
g3 smd transistor
SMD Transistor G6
SMD Transistor Marking Code S7
g3 smd transistor view
TRANSISTOR SMD MARKING CODE GFs
fet diode date sheet
FET MARKING CODE s5
smd transistor g3
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Untitled
Abstract: No abstract text available
Text: BG5412K Dual N-Channel MOSFET Tetrode • Designed for input stages of 2 band tuners 4 5 6 • Two AGC amplifiers in one single package, with on-chip internal switch 1 2 3 • Only one switching line to control both FETs • Integrated gate protection diodes
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BG5412K
OT363
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BCR108S
Abstract: BG5412K FET marking code
Text: BG5412K Dual N-Channel MOSFET Tetrode • Designed for input stages of 2 band tuners 4 5 6 • Two AGC amplifiers in one single package, with on-chip internal switch 1 2 3 • Only one switching line to control both FETs • Integrated gate protection diodes
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BG5412K
OT363
BCR108S
BG5412K
FET marking code
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200 Amp mosfet
Abstract: mosfet tetrode BCR108S BG5412K FET marking code
Text: BG5412K Dual N-Channel MOSFET Tetrode Preliminary • Designed for input stages of 2 band tuners 4 5 6 • Two AGC amplifiers in one single package, with on-chip internal switch 1 2 3 • Only one switching line to control both FETs • Integrated gate protection diodes
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BG5412K
BG5421K
OT363
200 Amp mosfet
mosfet tetrode
BCR108S
BG5412K
FET marking code
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Untitled
Abstract: No abstract text available
Text: UNISONIC TECHNOLOGIES CO., LTD L8200 Preliminary LINEAR INTEGRATED CIRCUIT CONFIDENTIAL, SUPPLIDE UNDE NDA SINGLE LNB-BIAS, CONTROL AND POWER MANAGEMENT SOLUTION DESCRIPTION The UTC L8200 is a single chip power management and control solution for LNB’s. The highly integrate solution provides
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L8200
L8200
QW-R123-017
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91840E
Abstract: S/91840E
Text: LF PA K 56D BUK9K18-40E Dual N-channel TrenchMOS logic level FET 23 April 2013 Product data sheet 1. General description Dual logic level N-channel MOSFET in a LFPAK56D package using TrenchMOS technology. This product has been designed and qualified to AEC Q101 standard for use
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BUK9K18-40E
LFPAK56D
91840E
S/91840E
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Untitled
Abstract: No abstract text available
Text: LF PA K 56D BUK9K52-60E Dual N-channel TrenchMOS logic level FET 23 April 2013 Product data sheet 1. General description Dual logic level N-channel MOSFET in a LFPAK56D package using TrenchMOS technology. This product has been designed and qualified to AEC Q101 standard for use
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BUK9K52-60E
LFPAK56D
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Untitled
Abstract: No abstract text available
Text: LF PA K 56D BUK7K6R8-40E Dual N-channel TrenchMOS standard level FET 19 March 2013 Product data sheet 1. General description Dual standard level N-channel MOSFET in a LFPAK56D package using TrenchMOS technology. This product has been designed and qualified to AEC Q101 standard for use
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BUK7K6R8-40E
LFPAK56D
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Untitled
Abstract: No abstract text available
Text: LF PA K 56D BUK9K52-60E Dual N-channel TrenchMOS logic level FET 17 June 2013 Product data sheet 1. General description Dual logic level N-channel MOSFET in a LFPAK56D package using TrenchMOS technology. This product has been designed and qualified to AEC Q101 standard for use
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BUK9K52-60E
LFPAK56D
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Untitled
Abstract: No abstract text available
Text: LF PA K 56D BUK9K89-100E Dual N-channel TrenchMOS logic level FET 23 April 2013 Product data sheet 1. General description Dual logic level N-channel MOSFET in a LFPAK56D package using TrenchMOS technology. This product has been designed and qualified to AEC Q101 standard for use
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BUK9K89-100E
LFPAK56D
referen10
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Untitled
Abstract: No abstract text available
Text: LF PA K 56D BUK9K29-100E Dual N-channel TrenchMOS logic level FET 28 March 2013 Product data sheet 1. General description Dual logic level N-channel MOSFET in a LFPAK56D package using TrenchMOS technology. This product has been designed and qualified to AEC Q101 standard for use
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BUK9K29-100E
LFPAK56D
referen10
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BF1009SR
Abstract: No abstract text available
Text: BF1009SR Dual - MOS FET Monolithic Integrated Circuit For low noise, high gain controlled input stages up to 1GHz Operating voltage 9V Integrated stabilized bias network Drain AGC HF Input G2 G1 HF Output + DC GND EHA07215 ESD: Electrostatic discharge sensitive device, observe handling precaution!
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BF1009SR
EHA07215
OT143R
Dec-04-2002
200MHz
BF1009SR
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BF1005R
Abstract: No abstract text available
Text: BF1005R Dual - MOS FET Monolithic Integrated Circuit For low noise, high gain controlled input stages up to 1GHz Operating voltage 5V Integrated stabilized bias network Drain AGC HF Input G2 G1 HF Output + DC GND EHA07215 ESD: Electrostatic discharge sensitive device, observe handling precaution!
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BF1005R
EHA07215
OT143R
Nov-07-2001
200MHz
BF1005R
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Untitled
Abstract: No abstract text available
Text: LF PA K 56D BUK7K5R1-30E Dual N-channel TrenchMOS standard level FET 19 April 2013 Product data sheet 1. General description Dual standard level N-channel MOSFET in a LFPAK56D package using TrenchMOS technology. This product has been designed and qualified to AEC Q101 standard for use
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BUK7K5R1-30E
LFPAK56D
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LFPAK56D
Abstract: BUK9K35-60E defect ppm
Text: LF PA K 56D BUK9K35-60E Dual N-channel TrenchMOS logic level FET 23 April 2013 Product data sheet 1. General description Dual logic level N-channel MOSFET in a LFPAK56D package using TrenchMOS technology. This product has been designed and qualified to AEC Q101 standard for use
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BUK9K35-60E
LFPAK56D
BUK9K35-60E
defect ppm
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72540E
Abstract: No abstract text available
Text: LF PA K 56D BUK7K25-40E Dual N-channel TrenchMOS standard level FET 23 April 2013 Product data sheet 1. General description Dual standard level N-channel MOSFET in a LFPAK56D package using TrenchMOS technology. This product has been designed and qualified to AEC Q101 standard for use
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BUK7K25-40E
LFPAK56D
72540E
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BF1005SR
Abstract: marking NZs
Text: BF1005SR Dual - MOS FET Monolithic Integrated Circuit For low noise, high gain controlled input stages up to 1GHz Operating voltage 5V Integrated stabilized bias network Drain AGC HF Input G2 G1 HF Output + DC GND EHA07215 ESD: Electrostatic discharge sensitive device, observe handling precaution!
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BF1005SR
EHA07215
OT143R
Oct-19-2001
200MHz
BF1005SR
marking NZs
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