parallel triac
Abstract: 5v DRIVE TRIAC GATE t410 TRANSISTOR low voltage triacs TRIAC SW triac parallel triacs Triac application note triac commutation triac drive circuit
Text: APPLICATION NOTE TRIAC & MICROCONTROLLERS : THE EASY CONNECTION Ph. RABIER The aim of this note is to show how to connect an SGS-THOMSON triac and an SGS-THOMSON microcontroller. Figure 2 : Conventional drive in the 2nd and 3rd quadrants. I - CONVENTIONAL SOLUTION
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02PHR358
parallel triac
5v DRIVE TRIAC GATE
t410 TRANSISTOR
low voltage triacs
TRIAC SW
triac
parallel triacs
Triac application note
triac commutation
triac drive circuit
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5v DRIVE TRIAC GATE
Abstract: t410 TRANSISTOR parallel triac parallel triacs sgs Thomson Triac triac static switch SGS Transistor TRIAC SW Triac application note triac for microcontroller
Text: APPLICATION NOTE TRIAC & MICROCONTROLLERS : THE EASY CONNECTION Ph. RABIER The aim of this note is to show how to connect an SGS-THOMSON triac and an SGS-THOMSON microcontroller. Figure 2 : Conventional drive in the 2nd and 3rd quadrants. I - CONVENTIONAL SOLUTION
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02PHR358
5v DRIVE TRIAC GATE
t410 TRANSISTOR
parallel triac
parallel triacs
sgs Thomson Triac
triac static switch
SGS Transistor
TRIAC SW
Triac application note
triac for microcontroller
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CY7C964
Abstract: No abstract text available
Text: 4.5 CY7C964 Operation 4.5.1 Overview The CY7C964 is a generalĆpurpose bus interface device that provides seamless support for the entire family of VMEbus interface controllers. The part is also suitable for many other Figure 4-3 generalĆpurpose bus interface applications.
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CY7C964
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RDRAM SOP
Abstract: RDRAM cross reference direct rdram rac
Text: VIS VG5612816AU VG5614418AU 128Mb/144Mb Direct Rambus Dynamic RAM Preliminary Current and Temperature Control samples the last calibration packet and adjusts its IOL current value. Figure 50 shows an example of a transaction which performs current control calibration. It is necessary to perform this
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VG5612816AU
VG5614418AU
128Mb/144Mb
1G5-0159
RDRAM SOP
RDRAM cross reference
direct rdram rac
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TC6358TB
Abstract: TX3922 T40 N03 smartmedia controller 1999 AJ08 MROMA14 t40 N06 32KHz PLL PCLR1 AG09
Text: TC6358TB TOSHIBA COMPANION CHIP FOR TX3922 PLUM2 1. General Description The PLUM2 is a companion chip for TX3922. The PLUM2 is connected to TX3922 to build advanced portable information terminal systems. Figure 1 shows a block diagram of PLUM2. The PLUM2 consists of a LCD / CRT controller, PCMCIA
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TC6358TB
TX3922
TX3922.
TX3922
16bit
TC6358TB
T40 N03
smartmedia controller 1999
AJ08
MROMA14
t40 N06
32KHz PLL
PCLR1
AG09
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transistor J1x
Abstract: AD8348 AD8348-EVAL figure t41 ETC1-1-13 LK11 SW11 ETK4-2T
Text: AD8348 Evaluation Board EVAL-AD8348EB BOARD DESCRIPTION Figure 1 shows the schematic for the EVAL-AD8348EB. Note that uninstalled components are indicated with the OPEN designation. The board is powered by a single supply in the range of 2.7 V to 5.5 V. Table 1 details the various configuration
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AD8348
EVAL-AD8348EB
EVAL-AD8348EB.
C04468
transistor J1x
AD8348-EVAL
figure t41
ETC1-1-13
LK11
SW11
ETK4-2T
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CY7C964
Abstract: No abstract text available
Text: 4.5 CY7C964 Operation 4.5.1 Overview The CY7C964 is a general-purpose bus interface device that provides seamless support for the entire family of VMEbus interface controllers. The part is also suitable for many other general-purpose bus interface applications. Figure 4-3 is the block diagram of the device,
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CY7C964
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Untitled
Abstract: No abstract text available
Text: T410H High temperature 4 A sensitive TRIACs Features A2 • Medium current TRIAC ■ Logic level sensitive TRIAC ■ 150 °C max. Tj turn-off commutation ■ Clip bounding ■ RoHS 2002/95/EC compliant package G A1 Applications A2 ■ The T410H is designed for the control of AC
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T410H
2002/95/EC)
T410H
O-220AB
T410H-6T
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T410H-6T
Abstract: T410H
Text: T410H High temperature 4 A sensitive TRIACs Features A2 • Medium current TRIAC ■ Logic level sensitive TRIAC ■ 150 °C max. Tj turn-off commutation ■ Clip bounding ■ RoHS 2002/95/EC compliant package G A1 Applications A2 ■ The T410H is designed for the control of AC
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T410H
2002/95/EC)
T410H
O-220AB
T410H-6T
T410H-6T
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inmos T414
Abstract: inmos T400 12u-1919-g19 25f5 T400 600 inmos transputer T425 T400 clock T800 transputer AD T805 IMS T414
Text: IMS T400 Low cost 32-bit transputer FEATURES H 32 bit architecture H 50 ns internal cycle time H 20 MHz only H 20 MIPS peak instruction rate H 10 MIPS sustained instruction rate H Pin compatible with IMS T805, IMS T800, IMS T425 and IMS T414 H 2 Kbytes on-chip static RAM
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32-bit
inmos T414
inmos T400
12u-1919-g19
25f5
T400 600
inmos transputer T425
T400 clock
T800 transputer
AD T805
IMS T414
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T425
Abstract: T400 T414 T800 T805 inmos transputer T425 T800 transputer IMST425
Text: IMS T425 32-bit transputer FEATURES 32 bit architecture 40 ns internal cycle time 25 MIPS peak instruction rate Pin compatible with IMS T805, IMS T800, IMS T400 and IMS T414 Debugging support 4 Kbytes on-chip static RAM System Services 100 Mbytes/sec sustained data rate to internal
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32-bit
T425
T400
T414
T800
T805
inmos transputer T425
T800 transputer
IMST425
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PEB 2256 HV
Abstract: No abstract text available
Text: 1 .0 Pin Assignments The RS8398 is packaged in a 208-pin Quad Flat Pack MQFP . A pinout diagram o f this device is illustrated in Figure 1-1. Figure 1-2 details a RS8398 Logic Diagram. Pin labels, names, input/output functions, and descriptions are provided
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RS8398
208-pin
D-238
N8398DSA
RS8398
GQ33T7S
D-239
PEB 2256 HV
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smd code marking a3a
Abstract: GDFP2-F16 SMD a3a smd code marking JL marking 2YP qml-38535 CQCC1-N20 FORM2233 GDIP1-T16
Text: REVISIONS LTR DESCRIPTION DATE YR-MO-DA APPROVED Added device type 02. Editorial changes throughout. 92-09-24 M. A. FRYE Add case outline F. Make changes to 1.2.2,1.3, and FIGURE 1. Changes in accordance with N.O.R. 5962-R066-94. 93-12-16 M. A. FRYE Add case outline E. Make changes to 1.2.2,1.3, FIGURE 1, and
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5962-R066-94.
smd code marking a3a
GDFP2-F16
SMD a3a
smd code marking JL
marking 2YP
qml-38535
CQCC1-N20
FORM2233
GDIP1-T16
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Untitled
Abstract: No abstract text available
Text: SARA Chipset Technical Manual Segmentation SARA Hardware Description Chapter 3. Hardware Description 3.1 Segmentation SARA Hardware Description 3.1.1 Segmentation SARA Internal Block Description Figure 3-1 shows a block diagram of the Segmentation SARA chip.
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DDD23D1
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Til 322A
Abstract: FFD11 280/Til 322A
Text: S A R A Chipset Technical Manual Segmentation SARA Hardware Description Chapter 3. Hardware Description 3.1 Segmentation SARA Hardware Description 3.1.1 Segmentation SARA Internal Block Description Figure 3-1 shows a block diagram of the Segmentation S A R A chip.
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3-27B.
3-28B.
Til 322A
FFD11
280/Til 322A
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Untitled
Abstract: No abstract text available
Text: lntel386TM EX EMBEDDED MICROPROCESSOR 6.0 AC SPECIFICATIONS Table 7 lists output delays, input setup requirements, and input hold requirements. All AC specifications are relative to the CLK2 rising edge crossing the Vcc/2 level. Figure 6 shows the measurement points for AC
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lntel386TM
Ht114
-------Ht113
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fe3001
Abstract: No abstract text available
Text: FE3001 WESTERN DIGITAL Figure 2. FE300I Block Diagram AT Control Logic I FE3001 WESTERN DIGITAL 84 1 CLK16 CLKHS 83 CLK14 55 56 RESIN PROCLK SYSCLK DMACLK TMRCLK PCLK PCLK ftÉSÓPU CLK287 ÒLYWR DMAMR RESET ÖNBRDL" 50 CPURES 51 MNIO MÉMC316 IOCS 16 ¿EROWS
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FE3001
FE300I
CLK14
CLK16
CLK287
MC316
fe3001
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I82365
Abstract: No abstract text available
Text: TO SH IBA TC6358TB TOSHIBA COMPANION CHIP FOR TX3922 PLUM2 1. General Description The PLUM2 is a companion chip for TX3922. The PLUM2 is connected to TX3922 to build advanced portable information terminal systems. Figure 1 shows a block diagram of PLUM2. The PLUM2 consists of a LCD / CRT controller, PCMCIA
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TC6358TB
TX3922
TX3922.
TX3922
16bit
I82365
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AT-41472
Abstract: No abstract text available
Text: AT-41472 Up to 1 GHz Low Noise ' Silicon Bipolar Transistor warn HEWLETT mLtiM PACKARD Features • • • • TO-72 Package Low Noise Figure: 1.3 dB typical at 0.5 GHz 2.0 dB typical at 1.0 GHz High Associated Gain: 14.0 dB typical at 0.5 GHz 10.0 dB typical at 1.0 GHz
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AT-41472
T-41472
ent072
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PIC16CR54
Abstract: No abstract text available
Text: M ic r o c h ip P IC 1 6 C R 5 4 ROM-Based 8-Bit CMOS Microcontroller FEATURES FIGURE A - PIN CONFIGURATION High-Performance RISC-like CPU PDIP, SOIC, CERDIP W indow • Only 33 single word instructions to learn • All single cycle instructions 200ns except for
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200ns)
200ns
12-bit
DS30075E-page
PIC16CR54
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T4148
Abstract: AT-41486 AVANTEK transistor Tbb 38 Avantek UA-152
Text: AVANTEK INC EOE D avan tek • limitt 1 AT-41486 Up to 6 GHz Low Noise Silicon Bipolar Transistor Avantek 86 Plastic Package Features • Low Noise Figure: 1.4 d B typical at 1.0 GHz 1.7 d B typical at 2.0 GHz • High Associated Gain: 18.0 dB typical at 1.0 GHz
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AT-41486
T4148
AVANTEK transistor
Tbb 38
Avantek UA-152
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Untitled
Abstract: No abstract text available
Text: tC e l t o n e M-957 DTMF Receiver T he Teltone M -957 see Figure 1 com bines switched-capacitor and digital frequency m easuring techniques to decode D ual-Tone M ultifrequency (DTM F) signals to four-bit binary data. D ial tone rejection and 60-H z noise rejection filters are
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M-957
22-pin
M-957-01
5-through-12volt
22121-20th
98021-44C8
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CE121
Abstract: No abstract text available
Text: Thal H E W L E T T m iftM P A C K A R D 0.5 - 6 GHz Low Noise GaAs MMIC Amplifier Technical Data MGA-86563 Featu res • Ultra-M iniature Package • Internally Biased, Single +5 V Supply 1 4 mA • 1.6 dB Noise Figure a t 2 .4 GHz • 2 1 .8 dB Gain a t 2 .4 GHz
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MGA-86563
OT-363
MGA-86563
OT-363
OT-143.
0D1643T
CE121
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4116 DRAM 16Kx1
Abstract: 82C206 82C558
Text: 82C556/82C557/82C558 Figure 2-3 82C557 SYSC Block Diagram I R ES ET PW RG D CLK ECLK LCLK HA[31:3] BE[7:0]# M /IO # D/C# W /R # /IN V /D IR TYO AD S # BRDY# NA# KEN #/LM EM # EADS#/(W B/W T#) HITM # CACHE# SM IACT# EC D OE# O C D O E# ECAWE#/CACSOO# OCAW E#/CACS1 O#
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82C556/82C557/82C558
82C557
4116 DRAM 16Kx1
82C206
82C558
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