FLIP FLOP 945 Search Results

master slave jk flip flop

Abstract: EL35 MC10EP35 MC10EP35D MC10EP35DR2
Contextual Info: MC10EP35 JK Flip Flop The MC10EP35 is a higher speed/low voltage version of the EL35 JK flip flop. The J/K data enters the master portion of the flip flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The reset pin is

MC100EP35

Contextual Info: MC10EP35, MC100EP35 3.3V / 5VĄECL JK Flip Flop The MC10/100EP35 is a higher speed/low voltage version of the EL35 JK flip flop. The J/K data enters the master portion of the flip flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The reset pin is

Toggle flip flop IC

Abstract: flip flop 945 flip flop j k
Contextual Info: MOTOROLA Order this document by MC10EP35/D SEMICONDUCTOR TECHNICAL DATA Product Preview MC10EP35 «IK Flip Flop The M C10EP35 is a higher speed/low voltage version of the EL35 JK flip flop. The J/K data enters the master portion of the flip flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a

EP29

Abstract: MC100EP29 MC10EP29 QFN-20 TSSOP-20 TSSOP20 FOOTPRINT
Contextual Info: MC10EP29, MC100EP29 3.3V / 5V ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset http://onsemi.com Description The MC10/100EP29 is a dual master-slave flip-flop. The device features fully differential Data and Clock inputs as well as outputs.

QFN-20

Abstract: EP29 MC100EP29 MC10EP29 TSSOP-20
Contextual Info: MC10EP29, MC100EP29 3.3V / 5V ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset http://onsemi.com Description The MC10/100EP29 is a dual master-slave flip-flop. The device features fully differential Data and Clock inputs as well as outputs.

HEP51

Abstract: KEP51 MC100 MC100EP51 MC10EP51 HEP-51
Contextual Info: MC10EP51, MC100EP51 Product Preview D Flip Flop with Set and Reset The MC10/100EP51 is a differential clock D flip-flop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices. The reset input is an asynchronous, level triggered signal. Data

Contextual Info: MC10EP131 Product Preview Quad D Flip Flop with Set, Reset and Differential Clock http://onsemi.com The MC10EP131 is a Quad Master–slaved D flip flop with common set and separate resets. The device is an expansion of the E131 with differential common clock and individual clock enables. With AC

Contextual Info: MC10EP131, MC100EP131 3.3V / 5VĄECL Quad D Flip Flop with Set, Reset, and Differential Clock The MC10/100EP131 is a Quad Master–slaved D flip flop with common set and separate resets. The device is an expansion of the E131 with differential common clock and individual clock enables.

HEP31

Abstract: MC10EP31 MC10EP31D MC10EP31DR2 LVEL31
Contextual Info: MC10EP31 D Flip Flop with Set and Reset The MC10EP31 is a D flip flop with set and reset. The device is pin and functionally equivalent to the EL31 and LVEL31 devices. With AC performance much faster than the EL31 and LVEL31 devices, the EP31 is ideal for applications requiring the fastest AC performance

MC10EP31

Contextual Info: MC10EP31 D Flip Flop with Set and Reset The MC10EP31 is a D flip flop with set and reset. The device is pin and functionally equivalent to the EL31 and LVEL31 devices. With AC performance much faster than the EL31 and LVEL31 devices, the EP31 is ideal for applications requiring the fastest AC performance

rtl micrologic 900

Abstract: fairchild 946 HALF ADDER fairchild rtl DTL Fairchild 946 DTL Fairchild 930 Fairchild 958 counter rtl decade counter RTL DTL logic 937 fairchild
Contextual Info: FAIRCHILD DIGITAL RTL/CTL DEVICE NO. Logic/Connection Diagram Package s Buffer F8 3F.5B 14 913 D Flip-Flop F6 3F.5B Counter Adapter F18 3F.5B 15 914 Dual 2-NOR F13 3F.5B 3 902 Flip-Flop F19 3F,5B 16 915 Dual 3-NOR F14 3F.5F 4 903 3-Input NOR F9 3F,5B 17 921

fairchild rtl

Abstract: 930 dtl DTL Fairchild 930 HALF ADDER fairchild 944 DTL Fairchild 945 944 dtl rtl micrologic DTL Logic nor gate Dtl 937
Contextual Info: FAIRCHILD DIGITAL RTL/CTL DEVICE NO. Logic/Connection Diagram Package s Buffer F8 3F.5B 14 913 D Flip-Flop F6 3F.5B Counter Adapter F18 3F.5B 15 914 Dual 2-NOR F13 3F.5B 3 902 Flip-Flop F19 3F,5B 16 915 Dual 3-NOR F14 3F.5F 4 903 3-Input NOR F9 3F,5B 17 921

HALF ADDER

Abstract: rtl micrologic 900 fairchild rtl Fairchild DTL 936 rtl nand gate 926 rtl micrologic fairchild micrologic 960 rtl inverter 4 bit binary half adder
Contextual Info: FAIRCHILD DIGITAL RTL/CTL DEVICE NO. Logic/Connection Diagram Package s Buffer F8 3F.5B 14 913 D Flip-Flop F6 3F.5B Counter Adapter F18 3F.5B 15 914 Dual 2-NOR F13 3F.5B 3 902 Flip-Flop F19 3F,5B 16 915 Dual 3-NOR F14 3F.5F 4 903 3-Input NOR F9 3F,5B 17 921

fairchild 946

Abstract: 930 dtl fairchild rtl DTL Fairchild 930 rtl micrologic 900 dtl 930 Fairchild 936 DTL Fairchild rtl micrologic fairchild 932
Contextual Info: FAIRCHILD DIGITAL RTL/CTL DEVICE NO. Logic/Connection Diagram Package s Buffer F8 3F.5B 14 913 D Flip-Flop F6 3F.5B Counter Adapter F18 3F.5B 15 914 Dual 2-NOR F13 3F.5B 3 902 Flip-Flop F19 3F,5B 16 915 Dual 3-NOR F14 3F.5F 4 903 3-Input NOR F9 3F,5B 17 921

KEP52

Abstract: HEP52 MC100EP52 bd 3055 MC10EP52 100EP52
Contextual Info: MC10EP52, MC100EP52 3.3V / 5VĄECL Differential Data and Clock D Flip-Flop The MC10EP/100EP52 is a differential data, differential clock D flip–flop. The device is pin and functionally equivalent to the EL52 device. Data enters the master portion of the flip–flop when the clock is

MC100EP35

Contextual Info: MC10EP35, MC100EP35 3.3V / 5V ECL JK Flip-Flop Description The MC10/100EP35 is a higher speed/low voltage version of the EL35 JK flip−flop. The J/K data enters the master portion of the flip−flop when the clock is LOW and is transferred to the slave, and

MC100EP52

Abstract: ECL D flip flop HEP52 248C2 KEP52 MC100 MC10EP52 g330
Contextual Info: MC10EP52, MC100EP52 3.3V / 5V ECL Differential Data and Clock D Flip-Flop Description The MC10EP/100EP52 is a differential data, differential clock D flip−flop. The device is pin and functionally equivalent to the EL52 device. Data enters the master portion of the flip−flop when the clock is

HEP52

Abstract: MC100EP52 hep52 transistor
Contextual Info: MC10EP52, MC100EP52 3.3V / 5V ECL Differential Data and Clock D Flip-Flop Description The MC10EP/100EP52 is a differential data, differential clock D flip−flop. The device is pin and functionally equivalent to the EL52 device. Data enters the master portion of the flip−flop when the clock is

master slave jk flip flop

Abstract: DFN8 J 3305 MC100EP35 code KP35 MC10EP35 EL35 HP35 KP35
Contextual Info: MC10EP35, MC100EP35 3.3V / 5V ECL JK Flip-Flop Description The MC10/100EP35 is a higher speed/low voltage version of the EL35 JK flip−flop. The J/K data enters the master portion of the flip−flop when the clock is LOW and is transferred to the slave, and

EP29

Abstract: MC100EP29 MC10EP29 EP-29
Contextual Info: MC10EP29, MC100EP29 3.3V / 5V ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset http://onsemi.com Description The MC10/100EP29 is a dual master−slave flip−flop. The device features fully differential Data and Clock inputs as well as outputs.

Contextual Info: MC10EP29, MC100EP29 3.3V / 5V ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset http://onsemi.com Description The MC10/100EP29 is a dual master−slave flip−flop. The device features fully differential Data and Clock inputs as well as outputs.

Contextual Info: MC10EP29, MC100EP29 3.3V / 5V ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset http://onsemi.com Description The MC10/100EP29 is a dual master−slave flip−flop. The device features fully differential Data and Clock inputs as well as outputs.

HEP51

Abstract: KEP51 MC100EP51 MC10EP51 LVEL51
Contextual Info: MC10EP51, MC100EP51 3.3V / 5VĄECL D Flip-Flop with Reset and Differential Clock The MC10/100EP51 is a differential clock D flip–flop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices. The reset input is an asynchronous, level triggered signal. Data

KEP31

Abstract: HEP31 MC100EP31 MC10EP31 HEP3 100EP31
Contextual Info: MC10EP31, MC100EP31 3.3V / 5VĄECL D Flip-Flop with Set and Reset The MC10/100EP31 is a D flip–flop with set and reset. The device is pin and functionally equivalent to the EL31 and LVEL31 devices. With AC performance much faster than the EL31 and LVEL31