FLIPFLOP Search Results

Contextual Info: TOSHIBA INTEGRATED CIRCUIT TECHNICAL DATA - C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC40H175 T C 4 0 H 1 7 5 P /F QUAD 0-TYPE FLIP-FLOP T h e T C 4 0 H 1 7 5 is a q u a d D - t y p e flipflop h a v i n g c o m m o n C L O C K a n d c o m m o n C L E A R inpuC.

IC 74HC112

Abstract: 74HC112
Contextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54/74HC112, CD54/74HCT112 Data sheet acquired from Harris Semiconductor SCHS141A Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised May 2000

74HC109

Contextual Info: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54/74HC109, CD54/74HCT109 Data sheet acquired from Harris Semiconductor SCHS140A Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised May 2000 Features

Contextual Info: son y. CXB1107Q/Q-Y Decision Circuit with Differential I/O Description Pin Assignm ent The CXB1107Q is an ECL ultra high speed monolithic Decision Circuit, which contains a D FlipFlop with High Gain Slicer at the input stage. Differential data input is amplified by the High

MM74C74J

Abstract: AN-90 C1995 J14A MM54C74 MM54C74J MM54C74N MM74C74 MM74C74N VCCe10V
Contextual Info: MM54C74 MM74C74 Dual D Flip-Flop General Description The MM54C74 MM74C74 dual D flip-flop is a monolithic complementary MOS CMOS integrated circuit constructed with N- and P-channel enhancement transistors Each flipflop has independent data preset clear and clock inputs

Contextual Info: TOSHIBA TC74HC174AP/AF/AFN HEX D-TVpe Flip-Flop with Clear The TC74HC174A is a high speed CMOS D-TYPE FLIPFLOP fabricated with silicon gate C 2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation.

54F398DM

Abstract: 54F398FM 54F398LM 74F398 74F398PC 74F398SC 74F399
Contextual Info: 54F 74F398  54F 74F399 Quad 2-Port Register General Description Features The ’F398 and ’F399 are the logical equivalents of a quad 2-input multiplexer feeding into four edge-triggered flipflops A common Select input determines which of the two 4-bit words is accepted The selected data enters the flipflops on the rising edge of the clock The ’F399 is the 16-pin

T74LS273B1

Abstract: LS273 T54LS273D2 T74LS273C1 LHAD
Contextual Info: T54LS273 T74LS273 S S 8-BIT REGISTER WITH CLEAR DESCRIPTION The T54LS273/T74LS273 is a high speed 8-Bit Re­ gister. The register consists of eight D-Type Flipflops with a Common Clock and an asynchronous active LOW Master Reset. This device is supplied in a 20-pin package featuring 0.3 inch lead spacing.

20 pin zif socket

Abstract: MS-012-AB 74ALS 74ALS377 N74ALS377D N74ALS377N TEXTOOL SOCKET DIP16 26 SIGNETICS TEXTOOL zif socket
Contextual Info: Signetics 74ALS377 Flip-Flop Octal D Flip-Flop With Enable Preliminary Specification ALS Products FEATURES • Ideal for addressable register applications • Enable for address and data syn­ chronization applications • Eight edge-triggered D-type flipflops

E530

Abstract: MS-012-AB 74ALS 74ALS273 N74ALS273D N74ALS273N 26 SIGNETICS
Contextual Info: Signetics 74ALS273 Flip-Flop Octal D Flip-Flop Preliminary Specification ALS Products FEATURES • Eight edge-triggered O-type flipflops • Buffered common clock • Buffered asynchronous Master Reset • See 'ALS377 for clock enable version TYPICAL fMAX

HC174

Abstract: CD54HC174 CD54HC174F3A CD54HCT174 CD74HC174 CD74HCT174 LS174 HCT17
Contextual Info: [ /Title CD74 HC174 , CD74 HCT17 4 /Subject (High Speed CMOS Logic Hex DType FlipFlop CD54HC174, CD74HC174, CD54HCT174, CD74HCT174 Data sheet acquired from Harris Semiconductor SCHS159C High-Speed CMOS Logic Hex D-Type Flip-Flop with Reset August 1997 - Revised October 2003

Contextual Info: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Data sheet acquired from Harris Semiconductor SCHS140C Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised May 2003

CD54HC174

Abstract: CD54HC174F3A CD54HCT174 CD74HC174 CD74HCT174 HC174 LS174
Contextual Info: [ /Title CD74 HC174 , CD74 HCT17 4 /Subject (High Speed CMOS Logic Hex DType FlipFlop CD54HC174, CD74HC174, CD54HCT174, CD74HCT174 Data sheet acquired from Harris Semiconductor SCHS159C High-Speed CMOS Logic Hex D-Type Flip-Flop with Reset August 1997 - Revised October 2003

CD54HC74

Abstract: CD54HC74F3A CD54HCT74 CD74HC74 CD74HCT74 CT74 HC74 HCT74
Contextual Info: [ /Title CD54H C74, CD74H C74, CD74H CT74 /Subject (Dual D FlipFlop with Set CD54HC74, CD74HC74, CD54HCT74, CD74HCT74 Data sheet acquired from Harris Semiconductor SCHS124D Dual D Flip-Flop with Set and Reset Positive-Edge Trigger January 1998 - Revised September 2003

Contextual Info: FAST CM O S O CTAL D FLIP-FLOP WITH CLEAR IDT54/74FCT273 IDT54/74FCT273A FEATURES: DESCRIPTION: • IDT54/74FCT273 equivalent to FAST speed; The IDT54/74FCT273 and IDT54/74FCT273A are octal D flipflops built using advanced CEMOS™, a dual metal CMOS tech­

74FCT273CT

Contextual Info: IDT54/74FCT273T/AT/CT FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • • • • The IDT54/74FCT273T/AT/CT are octal D flip-flops built using an advanced dual metal CMOS technology. The IDT54/ 74FCT273T/AT/CT have eight edge-triggered D-type flipflops with individual D inputs and O outputs. The common

Contextual Info: IDT74LVC1G79A 3.3V CMOS ADVANCE INFORMATION SINGLE POSITIVE-EDGETRIGGERED D-TYPE FLIPFLOP, 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: - This single positive-edge-triggered D-type flip-flop is built using advanced dual metal CMOS technology. The LVC1G79A is designed for 2.3V to 3.6V V cc operation.

CD74HC74M96

Abstract: CD74HC74MT CD74HC74M96E4 CD54HC74 CD54HC74F3A CD54HCT74 CD74HC74 CD74HCT74 CT74 HC74
Contextual Info: [ /Title CD54H C74, CD74H C74, CD74H CT74 /Subject (Dual D FlipFlop with Set CD54HC74, CD74HC74, CD54HCT74, CD74HCT74 Data sheet acquired from Harris Semiconductor SCHS124D Dual D Flip-Flop with Set and Reset Positive-Edge Trigger January 1998 - Revised September 2003

TC40H175P

Abstract: TC40H175 TC40H
Contextual Info: TOSHIBA INTEGRATED CIRCUIT TECHNICAL DATA . C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC40H175 TC40H175P/F QUAD 0-TYPE FLIP-FLOP The TC40H175 is a quad D-type flipflop having common CLOCK and common CLEAR input. The logical input applied to data input is

Contextual Info: [ /Title CD74 HC73, CD74 HCT73 /Subject (Dual J-K FlipFlop CD54HC73, CD74HC73, CD74HCT73 Data sheet acquired from Harris Semiconductor SCHS134E Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 - Revised September 2003 Features Description

CD74HCT107

Abstract: CD54HC107F3A CD54HCT107F3A CD74HC107E HC107 HCT10
Contextual Info: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54/74HC107, CD54/74HCT107 Data sheet acquired from Harris Semiconductor SCHS139B Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised December 2002

74VCX162374

Abstract: 74VCX162374MTD MTD48 VCX162374
Contextual Info: Preliminary Revised November 1999 74VCX162374 Low Voltage 16-Bit D-Type Flip-Flop with 3.6V Tolerant Inputs and Outputs and 26Ω Series Resistors in Outputs Preliminary General Description Features The VCX162374 contains sixteen non-inverting D-type flipflops with 3-STATE outputs and is intended for bus oriented

74AC377

Abstract: 74AC377MTC 74AC377SC 74AC377SJ 74ACT377 74ACT377MTC 74ACT377SC 74ACT377SJ
Contextual Info: 74AC377, 74ACT377 Octal D-Type Flip-Flop with Clock Enable Features General Description • ICC reduced by 50% The AC/ACT377 has eight edge-triggered, D-type flipflops with individual D inputs and Q outputs. The common buffered Clock CP input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW.

74ABT16374

Abstract: 74ABT16374CMTD 74ABT16374CSSC MS48A MTD48
Contextual Info: Revised January 1999 74ABT16374 16-Bit D-Type Flip-Flop with 3-STATE Outputs General Description Features The ABT16374 contains sixteen non-inverting D-type flipflops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock