FLIPFLOPS Search Results

54F398DM

Abstract: 54F398FM 54F398LM 74F398 74F398PC 74F398SC 74F399
Contextual Info: 54F 74F398  54F 74F399 Quad 2-Port Register General Description Features The ’F398 and ’F399 are the logical equivalents of a quad 2-input multiplexer feeding into four edge-triggered flipflops A common Select input determines which of the two 4-bit words is accepted The selected data enters the flipflops on the rising edge of the clock The ’F399 is the 16-pin

T74LS273B1

Abstract: LS273 T54LS273D2 T74LS273C1 LHAD
Contextual Info: T54LS273 T74LS273 S S 8-BIT REGISTER WITH CLEAR DESCRIPTION The T54LS273/T74LS273 is a high speed 8-Bit Re­ gister. The register consists of eight D-Type Flipflops with a Common Clock and an asynchronous active LOW Master Reset. This device is supplied in a 20-pin package featuring 0.3 inch lead spacing.

20 pin zif socket

Abstract: MS-012-AB 74ALS 74ALS377 N74ALS377D N74ALS377N TEXTOOL SOCKET DIP16 26 SIGNETICS TEXTOOL zif socket
Contextual Info: Signetics 74ALS377 Flip-Flop Octal D Flip-Flop With Enable Preliminary Specification ALS Products FEATURES • Ideal for addressable register applications • Enable for address and data syn­ chronization applications • Eight edge-triggered D-type flipflops

E530

Abstract: MS-012-AB 74ALS 74ALS273 N74ALS273D N74ALS273N 26 SIGNETICS
Contextual Info: Signetics 74ALS273 Flip-Flop Octal D Flip-Flop Preliminary Specification ALS Products FEATURES • Eight edge-triggered O-type flipflops • Buffered common clock • Buffered asynchronous Master Reset • See 'ALS377 for clock enable version TYPICAL fMAX

Contextual Info: FAST CM O S O CTAL D FLIP-FLOP WITH CLEAR IDT54/74FCT273 IDT54/74FCT273A FEATURES: DESCRIPTION: • IDT54/74FCT273 equivalent to FAST speed; The IDT54/74FCT273 and IDT54/74FCT273A are octal D flipflops built using advanced CEMOS™, a dual metal CMOS tech­

74FCT273CT

Contextual Info: IDT54/74FCT273T/AT/CT FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • • • • The IDT54/74FCT273T/AT/CT are octal D flip-flops built using an advanced dual metal CMOS technology. The IDT54/ 74FCT273T/AT/CT have eight edge-triggered D-type flipflops with individual D inputs and O outputs. The common

74VCX162374

Abstract: 74VCX162374MTD MTD48 VCX162374
Contextual Info: Preliminary Revised November 1999 74VCX162374 Low Voltage 16-Bit D-Type Flip-Flop with 3.6V Tolerant Inputs and Outputs and 26Ω Series Resistors in Outputs Preliminary General Description Features The VCX162374 contains sixteen non-inverting D-type flipflops with 3-STATE outputs and is intended for bus oriented

74AC377

Abstract: 74AC377MTC 74AC377SC 74AC377SJ 74ACT377 74ACT377MTC 74ACT377SC 74ACT377SJ
Contextual Info: 74AC377, 74ACT377 Octal D-Type Flip-Flop with Clock Enable Features General Description • ICC reduced by 50% The AC/ACT377 has eight edge-triggered, D-type flipflops with individual D inputs and Q outputs. The common buffered Clock CP input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW.

74ABT16374

Abstract: 74ABT16374CMTD 74ABT16374CSSC MS48A MTD48
Contextual Info: Revised January 1999 74ABT16374 16-Bit D-Type Flip-Flop with 3-STATE Outputs General Description Features The ABT16374 contains sixteen non-inverting D-type flipflops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock

Contextual Info: A I R C H I L D pe b m 7 J 9 Revised Aprii 1999 S E M ¡CONDUCTOR TM General Description Features T h e LC X16374 contains sixteen non-inverting D -type flipflops w ith 3-STATE outputs and is intended fo r bus oriented applications. The device is byte controlled. A buffered clock

LS 373

Abstract: als373
Contextual Info: AVG Semiconductors DDi Technical Data 373 Octal D-Type 3-State Transparent Latch DV74LS373 DV74ALS373 The DV74LS/74ALS373 circuits consist of eight latches with 3' state outputs for bus organized system applications. The flipflops appear transparent to the data data changes asynchronously . The high-impedance state and increased high-logic

004II

Contextual Info: H D 7 4 A C 1 0 9 / H D 7 4 A C T 1 0 9 *r;“ho„Po’ ”Ed°”T,s»«*d Description The HD74AC109/HD74ACT109 consists of two high­ speed completely independent transition clocked JK flipflops. The clocking operaiton is independent of rise and fall times of the clock waveform. The JK design allows

Contextual Info: High-Reliability Advanced CMOS Logic IC s_ m 37E D 430E571 O O S b l ? 11 2 I IHAS HARRIS SEIUCOND SECTOR Recent Additions CD54AC175/3A CD54ACT175/3A 0°l Quad D Flip-Flop with Reset The RCA CD54AC175 and CD54ACT175 are quad 0 flipflops with reset that utilize the new RCA ADVANCED CMOS

Contextual Info: 3.3V CMOS 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS AND BUS-HOLD FEATURES: - CMOS technology. The ALVCH162821 device can be used as two 10-bit flip-flops or one 20-bit flip-flop. The 20-bit flipflops are edge-triggered D-type flip-flops. On the positive

Contextual Info: & March 1993 74ACTQ18823 18-Bit D Flip-Flop with TRI-STATE Outputs General Description Features The ’ACTQ18823 contains eighteen non-inverting D flipflops with TRI-STATE outputs and is intended for bus orient­ ed applications. The device is byte controlled. A buffered

Contextual Info: Revised D ecem ber 1998 EMICQNDUCTGR tm 74ACTQ16374 16-Bit D-Type Flip-Flop with 3-STATE Outputs General Description Features T h e A C T Q 1 6374 contains sixteen non-inverting D-type flipflops w ith 3-STATE outputs and is intended fo r bus oriented applications. The device is byte controlled. A buffered clock

Contextual Info: 7 T S ci 2 3 7 un 1S 6 TH Q033b24 SGS-'mOMSOM ~ r-V é -o 7 V o T74LS378 IM [H ì [I[L i S ¥ [H ì® iO © i HEX PARALLEL D REGISTER WITH ENABLE • 8-BIT HIGH SPEED PARALLEL REGISTER ■ POSITIVE EDGE-TRIGGERED D-TYPE FLIPFLOPS ■ FULLY BUFFERED COMMON CLOCK AND

SO56-2

Abstract: IDT74ALVCH16721
Contextual Info: IDT74ALVCH16721 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS EXTENDED COMMERCIAL TEMPERATURE RANGE 3.3V CMOS 20-BIT FLIPFLOP WITH 3-STATE OUTPUTS AND BUS-HOLD FEATURES: IDT74ALVCH16721 DESCRIPTION: This 20-bit flip-flop is built using advanced dual metal CMOS technology. The 20 flip-flops of the ALVCH16721 are edge-triggered D-type flipflops with qualified clock storage. On the positive transition of the clock

Contextual Info: „ Revised April 1999 s e m ic o n d u c to r General Description Features T h e VCX16821 contains tw enty non-inverting D -type flipflops w ith 3-STATE outputs and is intended fo r bus oriented applications. • 1.6 5 V -3 .6 V V c c supply operation

DM74LS373

Abstract: DM74LS533 DM74LS533N DM74LS533WM MS-001 MS-013
Contextual Info: Revised March 2000 DM74LS533 Octal Transparent Latch with 3-STATE Outputs General Description Features The DM74LS533 consists of eight latches with 3-STATE outputs for bus organized system applications. The flipflops appear transparent to the data when Latch Enable

Contextual Info: Revised October 2004 74VCX16821 Low Voltage 20-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs General Description Features The VCX16821 contains twenty non-inverting D-type flipflops with 3-STATE outputs and is intended for bus oriented applications.

W16A

Abstract: 54279DMQB 54279FMQB C1995 DM74 DM74279 DM74279N J16A N16E
Contextual Info: 54279 DM74279 Quad Set-Reset Latch General Description This device contains four independent set-reset type flipflops with one Q output each Connection Diagram Dual-In-Line Package TL F 9785 – 1 Order Number 54279DMQB 54279FMQB or DM74279N NS Package Number J16A N16E or W16A

74ALVC16374

Abstract: 74ALVC16374GX 74ALVC16374MTD ALVC16374 MO-205 MTD48
Contextual Info: Revised May 2005 74ALVC16374 Low Voltage 16-Bit D-Type Flip-Flop with 3.6V Tolerant Inputs and Outputs General Description Features The ALVC16374 contains sixteen non-inverting D-type flipflops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock

LS373

Abstract: ALS373 LS-373 DV74ALS373
Contextual Info: DDT A VG Semiconductors Technical Data 373 Octal D-Type 3-State Transparent Latch DV74LS373 DV74ALS373 The DV74LS/74ALS373 circuits consist of eight latches with 3state outputs for bus organized system applications. The flipflops appear transparent to the data data changes asynchronously . The high-impedance state and increased high-logic