FPLA APPLICATIONS Search Results

22V10

Contextual Info: CHAPTER 2 M A P L 2 44 /2 68 ADVANCE INFO RM ATIO N 2.1 Introduction The MAPL244 and MAPL268 both integrate FPLA and PAL architec­ tures, which make it suitable for large sequential and combinato­ rial applications. The FPLA is similar to the MAPL28, thus allowing

Contextual Info: INTERNATIONAL CMOS TECHNOLOGY, INC. PEEL253 CMOS Programmable Electrically Erasable Logic Device Features • ADVANCED CMOS EEPROM TECHNOLOGY ■ FPLA ARCHITECTURE ■ COMPATIBLE PERFORMANCE — tpD = 30ns max, to E = 30ns max SUPERSET REPLACEMENT FOR PLS153

PEEL programming

Abstract: PEEL173 Erasable Programmable Logic Device 610 PLS173 8-12pF
Contextual Info: AMI PEEL 173 SEMICONDUCTORS CMOS Programmable Electrically Erasable Logic Device February 1993 Features General Description FPLA Architecture The AMI PEEL173 is a CMOS Programmable Electrically Erasable Logic device that provides a high-performance, low-power,

1B60

Abstract: PEEL programming msi ms 1772
Contextual Info: AMI PEEL 173 SEMICONDUCTORS CM O S Programmable Electrically Erasable Logic Device February 1993 Features General Description FPLA Architecture The AMI PEEL173 is a CMOS Programmable Electrically Erasable Logic device that provides a high-performance, low-power,

AL6002

Abstract: ic 8155 block diagram RT 8204
Contextual Info: GAL6002 Lattice High Performance E2CMOS FPLA Generic Array Logic Semiconductor Corporation FUNCTIONAL BLOCK DIAGRAM FEATURES • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 15ns Maximum Propagation Delay — 75MHz Maximum Frequency — 6.5ns Maximum Clock to Output Delay

AL6002

Abstract: lt 8232 ic 8155 block diagram lt 8219 pin diagram of 8203 LT 8216 al600 lt 8227 LT 8233 lt 8239
Contextual Info: GAL6002 Lattica High Performance E2CMOS FPLA Generic Array Logic Semiconductor Corporation FEATURES FUNCTIONAL BLOCK DIAGRAM • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 15ns Maximum Propagation Delay — 75MHz Maximum Frequency — 6.5ns Maximum Clock to Output Delay

lt 8224

Abstract: lt 8232 lt 8227 lt 8239 LT 8195 lt 8225 LT 8216 fn521 lt 8220 ep 8212
Contextual Info: Specifications GAL6002 GAL6002 High Performance E2CMOS FPLA Generic Array Logic FEATURES FUNCTIONAL BLOCK DIAGRAM • HIGH PERFORMANCE E CMOS TECHNOLOGY — 15ns Maximum Propagation Delay — 75MHz Maximum Frequency — 6.5ns Maximum Clock to Output Delay

lt 8232

Abstract: LT 8233 lt 8217 LT 8209 LT 8223 lt 8219 GAL6002 GAL6002B-15LJ GAL6002B-15LP R/diode lt 8232
Contextual Info: Specifications GAL6002 GAL6002 High Performance E2CMOS FPLA Generic Array Logic FUNCTIONAL BLOCK DIAGRAM FEATURES • HIGH PERFORMANCE E CMOS TECHNOLOGY — 15ns Maximum Propagation Delay — 75MHz Maximum Frequency — 6.5ns Maximum Clock to Output Delay

GAL6001

Abstract: GAL6001B-30LJ GAL6001B-30LP 8178
Contextual Info: Specifications GAL6001 GAL6001 High Performance E2CMOS FPLA Generic Array Logic FEATURES FUNCTIONAL BLOCK DIAGRAM ICLK • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 30ns Maximum Propagation Delay — 27MHz Maximum Frequency — 12ns Maximum Clock to Output Delay

GAL6001

Abstract: GAL6001B-30LJ GAL6001B-30LP
Contextual Info: Specifications GAL6001 GAL6001 High Performance E2CMOS FPLA Generic Array Logic FEATURES FUNCTIONAL BLOCK DIAGRAM ICLK • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 30ns Maximum Propagation Delay — 27MHz Maximum Frequency — 12ns Maximum Clock to Output Delay

273-12/PEELT273-15

Abstract: PEEL22CV10ZP-25
Contextual Info: Preliminary Information INC. PEEL 273-12/PEELT273-15 CMOS Programmable Electrically Erasable Logic Device Features • ADVANCED CM OS EEPROM TECHNOLOGY ■ FPLA ARCHITECTURE ■ LOW POW ER CONSUMPTION ■ SUPERSET REPLACEM ENT FOR PLS173 — — — —

Contextual Info: Lattice GAL6001B High Performance E2CMOS FPLA Generic Array Logic •■■■ FEATURES FUNCTIONAL BLOCK DIAGRAM • HIGH PERFORMANCE E’CMOS* TECHNOLOGY — 30ns Maximum Propagation Delay — 27MHz Maximum Frequency — 12ns Max. Clock to Output Delay

ta 8221 H

Abstract: GAL6001 e2cmos technology GAL6001B-30LJ GAL6001B-30LP
Contextual Info: GAL6001 High Performance E2CMOS FPLA Generic Array Logic Features Functional Block Diagram • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 30ns Maximum Propagation Delay — 27MHz Maximum Frequency — 12ns Maximum Clock to Output Delay — TTL Compatible 16mA Outputs

lt 8232

Abstract: LT 8216 LT 8215 LT 8209 lt 8227 lt 8221 lt 8225 lt 8239 lt 8219 lt 8224
Contextual Info: Specifications GAL6002 GAL6002 High Performance E2CMOS FPLA Generic Array Logic FUNCTIONAL BLOCK DIAGRAM FEATURES • HIGH PERFORMANCE E CMOS TECHNOLOGY — 15ns Maximum Propagation Delay — 75MHz Maximum Frequency — 6.5ns Maximum Clock to Output Delay

signetics 82s100

Abstract: 82S100-I fpla 82S100 82S101 825100 82S100 programming 82S100/BXA
Contextual Info: s ig n o tic s BIPOLAR FIELD-PROGRAMMABLE LOGIC ARRAY 16X8X48 FPLA 82S101 (OPEN COLLECTOR) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 82S100 (TRI-STATE) O B JEC T IV E SPECIFICATION A P R IL 1975 825100 825101 DIGITAL 8000 SERIES TTL/MEMORY DESCRIPTION PIN CONFIGURATION

GAL6001-30P

Abstract: ic 8155 block diagram GAL6001-30J
Contextual Info: Lattice GAL6002B High Performance E2CMOS FPLA Generic Array Logic FUNCTIONAL BLOCK DIAGRAM FEATURES • HIGH PERFORMANCE E*CMOS* TECHNOLOGY — 15ns Maximum Propagation Delay — 75MHz Maximum Frequency — 6.5ns Max. Clock to Output Delay — TTL Compatible 16mA Outputs

LT 8232

Abstract: LT 8215 lt 8225 LT 8224 lt 8220 lt 8228 lt 8239 LT 8229 LT 8233 lt 8227
Contextual Info: GAL6002 High Performance E2CMOS FPLA Generic Array Logic Features Functional Block Diagram ICLK • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 15ns Maximum Propagation Delay — 75MHz Maximum Frequency — 6.5ns Maximum Clock to Output Delay — TTL Compatible 16mA Outputs

GAL6001

Abstract: GAL6001B-30LJ GAL6001B-30LP
Contextual Info: GAL6001 High Performance E2CMOS FPLA Generic Array Logic Features Functional Block Diagram • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 30ns Maximum Propagation Delay — 27MHz Maximum Frequency — 12ns Maximum Clock to Output Delay — TTL Compatible 16mA Outputs

GAL6002

Abstract: MAX235 T-FLIP FLOPS maxim rs232 multiplexer
Contextual Info: GAL 6002: 4-to-1 RS232 Port Multiplexer Figure 1. TxD During Single Byte Transfer Introduction The GAL6002 is the most versatile 24-pin PLD available today. Its FPLA architecture offers buried macrocells, D/E registers, programmable clocks and dedicated input

lt 8232

Abstract: LT 8215 lt 8219 lt 8239 LT 8209 lt 8217 lt 8227 lt 8220 LT 8233 lt 8221
Contextual Info: GAL6002 High Performance E2CMOS FPLA Generic Array Logic Features Functional Block Diagram ICLK • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 15ns Maximum Propagation Delay — 75MHz Maximum Frequency — 6.5ns Maximum Clock to Output Delay — TTL Compatible 16mA Outputs

8256 ap

Contextual Info: Lattice GAL6002B High Performance E2CMOS FPLA Generic Array Logic FEATURES FUNCTIONAL BLOCK DIAGRAM • HIGH PERFORMANCE E*CMOS* TECHNOLOGY — 15ns Maximum Propagation Delay — 75MHz Maximum Frequency — 6.5ns Max. Clock to Output Delay — TTL Compatible 16mA Outputs

GAL6002

Abstract: MAX235
Contextual Info: GAL 6002: 4-to-1 RS232 Port Multiplexer Figure 1. TxD During Single Byte Transfer Introduction The GAL6002 is the most versatile 24-pin PLD available today. Its FPLA architecture offers buried macrocells, D/E registers, programmable clocks and dedicated input

Contextual Info: Lattice GAL6001 High Performance E2CMOS FPLA Generic Array Logic FEATURES FUNCTIONAL BLOCK DIAGRAM • HIGH PERFORMANCE E*CMOS* TECHNOLOGY — 30ns Maximum Propagation Delay — 27MHz Maximum Frequency — 12ns Max. Clock to Output Delay — TTL Compatible 16mA Output«

RT 8206

Abstract: GAL6001 GAL6001B-30LP
Contextual Info: GAL6001 Lattice! High Performance E2CMOS FPLA v Generic Array Logic FUNCTIONAL BLOCK DIAGRAM • HIGH PERFORMANCE E2CMOS TECHNOLOGY — — — — — 30ns Maximum Propagation Delay 27MHz Maximum Frequency 12ns Max. Clock to Output Delay TTL Compatible 16mA Outputs