FULLY BALANCED AMPLIFIERS Search Results

Contextual Info: pgU G EC PLESSEY DS3348-1.3 DA1501 S-BAND DOUBLE BALANCED MIXER The DA1501 is a broadband double balanced mixer for use from 2 to 4GHz using silicon schottky barrier diodes. It features small size and light weight together with fully hermetic SMA female connectors.

DS90C124

Contextual Info: DS90C241/DS90C124 5-35MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer General Description • User selectable clock edge for parallel data on both The DS90C241/DS90C124 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream

Contextual Info: General Description Features The DS25BR204 is a 3.125 Gbps 1:4 LVDS repeater optimized for high-speed signal routing and switching over lossy FR-4 printed circuit board backplanes and balanced cables. Fully differential signal paths ensure exceptional signal integrity and noise immunity.

DS25BR204

Abstract: DS25BR204TSQ STM-16
Contextual Info: General Description Features The DS25BR204 is a 3.125 Gbps 1:4 LVDS repeater optimized for high-speed signal routing and switching over lossy FR-4 printed circuit board backplanes and balanced cables. Fully differential signal paths ensure exceptional signal integrity and noise immunity.

DS90C124

Abstract: AEC-Q100 AN-1108 AN-1217 DS90C241 ISO10605 RGB666
Contextual Info: DS90C241/DS90C124 5-35MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer General Description • User selectable clock edge for parallel data on both The DS90C241/DS90C124 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream

Contextual Info: DS25BR150 DS25BR150 3.125 Gbps LVDS Buffer Literature Number: SNLS257D DS25BR150 3.125 Gbps LVDS Buffer General Description Features The DS25BR150 is a single channel 3.125 Gbps LVDS buffer optimized for high-speed signal transmission over printed circuit boards and balanced cables. Fully differential signal

DS25BR204

Abstract: DS25BR204TSQ STM-16
Contextual Info: General Description Features The DS25BR204 is a 3.125 Gbps 1:4 LVDS repeater optimized for high-speed signal routing and switching over lossy FR-4 printed circuit board backplanes and balanced cables. Fully differential signal paths ensure exceptional signal integrity and noise immunity.

DS25BR100

Abstract: DS25BR110 DS25BR120 DS25BR150 DS25BR150TSD STM-16 nc-5na
Contextual Info: DS25BR150 3.125 Gbps LVDS Buffer General Description Features The DS25BR150 is a single channel 3.125 Gbps LVDS buffer optimized for high-speed signal transmission over printed circuit boards and balanced cables. Fully differential signal paths ensure exceptional signal integrity and noise immunity.

DS90C124

Contextual Info: DS90UR241/DS90UR124 5-43 MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer General Description • User selectable clock edge for parallel data on both The DS90UR241/124 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with

DS90C124

Contextual Info: DS90UR241/DS90UR124 5-43 MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer General Description • User selectable clock edge for parallel data on both The DS90UR241/124 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with

Contextual Info: LMC568 www.ti.com SNAS559B – MAY 1999 – REVISED APRIL 2013 LMC568 Low Power Phase-Locked Loop Check for Samples: LMC568 FEATURES DESCRIPTION • • • • • • The LMC568 is an amplitude-linear phase-locked loop consisting of a linear VCO, fully balanced phase

High power led driver

Abstract: AN-1187 DS10BR150 DS10BR150TSD SDA08A
Contextual Info: DS10BR150 1.0 Gbps LVDS Buffer / Repeater General Description Features The DS10BR150 is a single channel 1.0 Gbps LVDS buffer optimized for high-speed signal transmission over lossy FR-4 printed circuit board backplanes and balanced cables. Fully differential signal paths ensure exceptional signal integrity

DS90C124

Abstract: AEC-Q100 AN-1217 DS90UR124 DS90UR241 ISO10605
Contextual Info: DS90UR241/DS90UR124 5-43 MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer General Description • User selectable clock edge for parallel data on both The DS90UR241/124 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with

RGB666

Abstract: LVDS connector 40 pins DS90C124 DS90UR124 giga media converter LVDS 30 pin connector cable LVDS connector 40 pins NAME SDI SERIALIZER SWITCHING NOISE SUPPRESSION OF LVDS SERIALIZER AEC-Q100
Contextual Info: DS90UR241/DS90UR124 5-43 MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer General Description • User selectable clock edge for parallel data on both The DS90UR241/124 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with

DS90C124

Abstract: AEC-Q100 AN-1108 AN-1217 DS90C241 ISO10605 RGB666
Contextual Info: DS90C241/DS90C124 5-35MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer General Description • User selectable clock edge for parallel data on both The DS90C241/DS90C124 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream

AN-1719

Abstract: ADC14DS105 LMH6550 LMH6551 LMH6552
Contextual Info: National Semiconductor Application Note 1719 Robert Malone, Mike Ewer September 2007 Fully Differential Feedback Amplifiers FDA such as National’s LMH6550, LMH6551 and the newly released LMH6552 are used to provide balanced low distortion amplification and level shifting to wide bandwidth differential signals. A simplified conceptual diagram of an FDA is shown in

Contextual Info: LMC568 www.ti.com SNAS559B – MAY 1999 – REVISED APRIL 2013 LMC568 Low Power Phase-Locked Loop Check for Samples: LMC568 FEATURES DESCRIPTION • • • • • • The LMC568 is an amplitude-linear phase-locked loop consisting of a linear VCO, fully balanced phase

DS90C124

Abstract: VBC48A AEC-Q100 AN-1108 AN-1217 DS90C241 ISO10605 RGB666
Contextual Info: DS90C241/DS90C124 5-35MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer General Description • User selectable clock edge for parallel data on both The DS90C241/DS90C124 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream

Contextual Info: 900 MHz ISM Band Analog RF Front End ADF9010 FUNCTIONAL BLOCK DIAGRAM 840 MHz to 960 MHz ISM bands Rx baseband analog low-pass filtering and PGA Integrated RF Tx upconverter Integrated integer-N PLL and VCO Integrated Tx PA preamplifier Differential fully balanced architectures

Contextual Info: LMC568 www.ti.com SNAS559B – MAY 1999 – REVISED APRIL 2013 LMC568 Low Power Phase-Locked Loop Check for Samples: LMC568 FEATURES DESCRIPTION • • • • • • The LMC568 is an amplitude-linear phase-locked loop consisting of a linear VCO, fully balanced phase

DS10CP152

Abstract: DS10CP152TMA M16A SOIC-16
Contextual Info: DS10CP152 1.5 Gbps 2X2 LVDS Crosspoint Switch General Description Features The DS10CP152 is a 1.5 Gbps 2x2 LVDS crosspoint switch optimized for high-speed signal routing and switching over lossy FR-4 printed circuit board backplanes and balanced cables. Fully differential signal paths ensure exceptional signal

Contextual Info: DS25CP152 3.125 Gbps LVDS 2x2 Crosspoint Switch General Description Features The DS25CP152 is a 3.125 Gbps 2x2 LVDS crosspoint switch optimized for high-speed signal routing and switching over lossy FR-4 printed circuit board backplanes and balanced cables. Fully differential signal paths ensure exceptional signal

Contextual Info: DS10CP152Q Automotive 1.5 Gbps 2X2 LVDS Crosspoint Switch General Description Features The DS10CP152Q is a 1.5 Gbps 2x2 LVDS crosspoint switch optimized for high-speed signal routing and switching over lossy FR-4 printed circuit board backplanes and balanced cables. Fully differential signal paths ensure exceptional signal

DS10BR254

Abstract: DS10BR254TSQ AN-1187 LLP-40
Contextual Info: DS10BR254 1.5 Gbps 1:4 LVDS Repeater General Description Features The DS10BR254 is a 1.5 Gbps 1:4 LVDS repeater optimized for high-speed signal routing and distribution over FR-4 printed circuit board backplanes and balanced cables. Fully differential signal paths ensure exceptional signal integrity and