HD74LV1GT Search Results

Hitachi DSA0076

Abstract: HD74LV1GT14A
Contextual Info: HD74LV1GT14A Inverter with Schmitt-trigger Input ADE-205-329C Z 4th. Edition April 2001 Description The HD74LV1GT14A is high speed CMOS schmitt-trigger inverter using silicon gate CMOS process. With CMOS low power dissipation, it provides high speed equivalent to LS–TTL series. The internal

Hitachi DSA0076

Abstract: HD74LV1GT04A
Contextual Info: HD74LV1GT04A Inverter ADE-205-327C Z 4th. Edition August 2000 Description The HD74LV1GT04A has an inverter in a 5 pin package. Low voltage and high speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power consumption extends the

Hitachi DSA0076

Abstract: HD74LV1GT02A
Contextual Info: HD74LV1GT02A 2–input NOR Gate ADE-205-326C Z 4th. Edition April 2000 Description The HD74LV1GT02A is high speed CMOS two input NOR gate using silicon gate CMOS process. With CMOS low power dissipation, it provides high speed equivalent to LS–TTL series. The internal circuit of

Hitachi DSA0076

Abstract: HD74LV1GT32A
Contextual Info: HD74LV1GT32A 2–input OR Gate ADE-205-330C Z 4th. Edition April 2000 Description The HD74LV1GT32A is high speed CMOS two input OR gate using silicon gate CMOS process. With CMOS low power dissipation, it provides high speed equivalent to LS–TTL series. The internal circuit of

HD74LV1GT126A

Abstract: HD74LV1GT126ACME HD74LV1GT126AVSE
Contextual Info: HD74LV1GT126A Bus Buffer Gate with 3–state Output / CMOS Logic Level Shifter REJ03D0124–0800Z Previous ADE-205-333F (Z Rev.8.00 Sep.25.2003 Description The HD74LV1GT126A has a bus buffer gate with 3–state output in a 5 pin package. Output is disabled

HD74LV1GT14ACME

Abstract: HD74LV1GT14AVSE HD74LV1GT14A marking up- RENESAS ADE-205-329D
Contextual Info: HD74LV1GT14A Inverter with Schmitt-trigger Input / CMOS Logic Level Shifter REJ03D0119–0600Z Previous ADE-205-329D (Z Rev.6.00 Sep.24.2003 Description The HD74LV1GT14A is high-speed CMOS schmitt-trigger inverter using silicon gate CMOS process. With CMOS low power dissipation, it provides high-speed equivalent to LS–TTL series. The internal

HD74LV1GT66A

Abstract: HD74LV1GT66ACME HD74LV1GT66AVSE PTSP0005ZC-A PUSN0005KA-A
Contextual Info: HD74LV1GT66A Analog Switch REJ03D0121-0800 Rev.8.00 Mar 21, 2008 Description The HD74LV1GT66A has an analog switch in a 5 pin package. Switch section has its enable input control C . Highlevel voltage applied to C turns on the switch section. Applications include signal gating, chopping, modulation, or

HD74LV1GT02A

Abstract: HD74LV1GT02ACME HD74LV1GT02AVSE PTSP0005ZC-A PUSN0005KA-A
Contextual Info: HD74LV1GT02A 2–input NOR Gate / CMOS Logic Level Shifter REJ03D0116-0900 Rev.9.00 Mar 21, 2008 Description The HD74LV1GT02A is high-speed CMOS two input NOR gate using silicon gate CMOS process. With CMOS low power dissipation, it provides high-speed equivalent to LS–TTL series. The internal circuit of three stages construction

Hitachi DSA0076

Abstract: HD74LV1GT66A
Contextual Info: HD74LV1GT66A Analog Switch ADE-205-565B Z 3rd. Edition October 2000 Description The HD74LV1GT66A has an analog switch in a 5 pin package. Switch section has its enable input control (C). High level voltage applied to C turns on the switch section. Applications include signal gating,

HD74LV1GT08ACME

Abstract: and gate cmos HD74LV1GT08AVSE HD74LV1GT08A
Contextual Info: HD74LV1GT08A 2–input AND Gate / CMOS Logic Level Shifter REJ03D0118–0800Z Previous ADE-205-328F (Z Rev.8.00 Sep.24.2003 Description The HD74LV1GT08A is high-speed CMOS two input AND gate using silicon gate CMOS process. With CMOS low power dissipation, it provides high-speed equivalent to LS–TTL series. The internal circuit of

HD74LV1GT00A

Abstract: HD74LV1GT00ACME HD74LV1GT00AVSE PTSP0005ZC-A PUSN0005KA-A
Contextual Info: HD74LV1GT00A 2–input NAND Gate / CMOS Logic Level Shifter REJ03D0115-0900 Rev.9.00 Mar 21, 2008 Description The HD74LV1GT00A is high-speed CMOS two input NAND gate using silicon gate CMOS process. With CMOS low power dissipation, it provides high-speed equivalent to LS–TTL series. The internal circuit of three stages construction

HD74LV1GT126A

Abstract: HD74LV1GT126ACME HD74LV1GT126AVSE PTSP0005ZC-A PUSN0005KA-A
Contextual Info: HD74LV1GT126A Bus Buffer Gate with 3–state Output / CMOS Logic Level Shifter REJ03D0124-0900 Rev.9.00 Mar 21, 2008 Description The HD74LV1GT126A has a bus buffer gate with 3–state output in a 5 pin package. Output is disabled when the associated output enable OE input is low. To ensure the high impedance state during power up or power down, OE

HD74LV1GT08A

Abstract: HD74LV1GT08ACME HD74LV1GT08AVSE PTSP0005ZC-A PUSN0005KA-A RENESAS marking code
Contextual Info: HD74LV1GT08A 2–input AND Gate / CMOS Logic Level Shifter REJ03D0118-0900 Rev.9.00 Mar 21, 2008 Description The HD74LV1GT08A is high-speed CMOS two input AND gate using silicon gate CMOS process. With CMOS low power dissipation, it provides high-speed equivalent to LS–TTL series. The internal circuit of three stages construction

HD74LV1GT125A

Abstract: HD74LV1GT125ACME HD74LV1GT125AVSE
Contextual Info: HD74LV1GT125A Bus Buffer Gate with 3–state Output / CMOS Logic Level Shifter REJ03D0123–0800Z Previous ADE-205-332F (Z Rev.8.00 Sep.24.2003 Description The HD74LV1GT125A has a bus buffer gate with 3–state output in a 5 pin package. Output is disabled

Hitachi DSA0076

Abstract: HD74LV1GT08A
Contextual Info: HD74LV1GT08A 2–input AND Gate ADE-205-328C Z 4th. Edition April 2000 Description The HD74LV1GT08A is high speed CMOS two input AND gate using silicon gate CMOS process. With CMOS low power dissipation, it provides high speed equivalent to LS–TTL series. The internal circuit of

HD74LV1GT04A

Abstract: HD74LV1GT04ACME HD74LV1GT04AVSE
Contextual Info: HD74LV1GT04A Inverter / CMOS Logic Level Shifter REJ03D0117–0800Z Previous ADE-205-327F (Z Rev.8.00 Sep.24.2003 Description The HD74LV1GT04A has an inverter in a 5 pin package. The input protection circuitry on this device allows over voltage tolerance on the input, allowing the device to be used as a logic–level translator from

HD74LV1GT86A

Abstract: HD74LV1GT86ACME HD74LV1GT86AVSE PTSP0005ZC-A PUSN0005KA-A
Contextual Info: HD74LV1GT86A 2–input Exclusive–OR Gate / CMOS Logic Level Shifter REJ03D0122-1000 Rev.10.00 Mar 21, 2008 Description The HD74LV1GT86A performs the Boolean functions Y = A ⊕ B or Y = AB + AB in positive logic. A common application is as a true / complement element. If one of the inputs is low, the other input will be reproduced in true

HD74LV1GT14A

Abstract: HD74LV1GT14ACME HD74LV1GT14AVSE PTSP0005ZC-A PUSN0005KA-A
Contextual Info: HD74LV1GT14A Inverter with Schmitt-trigger Input / CMOS Logic Level Shifter REJ03D0119-0700 Rev.7.00 Mar 21, 2008 Description The HD74LV1GT14A is high-speed CMOS schmitt-trigger inverter using silicon gate CMOS process. With CMOS low power dissipation, it provides high-speed equivalent to LS–TTL series. The internal circuit of three stages

HD74LV1GT32A

Abstract: HD74LV1GT32ACME HD74LV1GT32AVSE PTSP0005ZC-A PUSN0005KA-A
Contextual Info: HD74LV1GT32A 2–input OR Gate / CMOS Logic Level Shifter REJ03D0120-0900 Rev.9.00 Mar 21, 2008 Description The HD74LV1GT32A is high-speed CMOS two input OR gate using silicon gate CMOS process. With CMOS low power dissipation, it provides high-speed equivalent to LS–TTL series. The internal circuit of three stages construction

HD74LV1GT04A

Abstract: HD74LV1GT04ACME HD74LV1GT04AVSE PTSP0005ZC-A PUSN0005KA-A
Contextual Info: HD74LV1GT04A Inverter / CMOS Logic Level Shifter REJ03D0117-0900 Rev.9.00 Mar 21, 2008 Description The HD74LV1GT04A has an inverter in a 5 pin package. The input protection circuitry on this device allows over voltage tolerance on the input, allowing the device to be used as a logic–level translator from 3.0 V CMOS Logic to 5.0

cmos logic circuit

Abstract: HD74LV1GT86A HD74LV1GT86ACME HD74LV1GT86AVSE RENESAS MARKING AB
Contextual Info: HD74LV1GT86A 2–input Exclusive–OR Gate / CMOS Logic Level Shifter REJ03D0122–0900Z Previous ADE-205-331G (Z Rev.9.00 Sep.24.2003 Description The HD74LV1GT86A performs the Boolean functions Y = A ⊕ B or Y = AB + AB in positive logic. A common application is as a true / complement element. If one of the inputs is low, the other input will be

HD74LV1GT14A

Abstract: Hitachi DSA0015
Contextual Info: HD74LV1GT14A Inverter with Schmitt-trigger Input ADE-205-329B Z 3rd. Edition April 2000 Description The HD74LV1GT14A is high speed CMOS schmitt-trigger inverter using silicon gate CMOS process. With CMOS low power dissipation, it provides high speed equivalent to LS–TTL series. The internal

Contextual Info: HD74LV1GT66A Analog Switch REJ03D0121–0700Z Previous ADE-205-565E (Z Rev.7.00 Sep.25.2003 Description The HD74LV1GT66A has an analog switch in a 5 pin package. Switch section has its enable input control (C). High-level voltage applied to C turns on the switch section. Applications include signal gating,

Hitachi DSA0076

Abstract: HD74LV1GT125A
Contextual Info: HD74LV1GT125A Bus Buffer Gate with 3–state Output ADE-205-332B Z 3rd. Edition April 2000 Description The HD74LV1GT125A has a bus buffer gate with 3–state output in a 5 pin package. Output is disabled when the associated output enable (OE) input is high. To ensure the high impedance state during power up