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    I2C CONTROLLER WITH APB INTERFACE Search Results

    I2C CONTROLLER WITH APB INTERFACE Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TB67S539FTG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver/Bipolar Type/Vout(V)=40/Iout(A)=2/Clock Interface Visit Toshiba Electronic Devices & Storage Corporation
    TB67S141AFTG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver/Unipolar Type/Vout(V)=84/Iout(A)=3/Phase Interface Visit Toshiba Electronic Devices & Storage Corporation
    TB67S149AFTG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver/Unipolar Type/Vout(V)=84/Iout(A)=3/Clock Interface Visit Toshiba Electronic Devices & Storage Corporation
    TB67S549FTG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver/Bipolar Type/Vout(V)=40/Iout(A)=1.5/Clock Interface Visit Toshiba Electronic Devices & Storage Corporation
    SSM6J808R Toshiba Electronic Devices & Storage Corporation MOSFET, P-ch, -40 V, -7 A, 0.035 Ohm@10V, TSOP6F, AEC-Q101 Visit Toshiba Electronic Devices & Storage Corporation

    I2C CONTROLLER WITH APB INTERFACE Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    APB to I2C interface

    Abstract: i2c controller with apb interface AMBA APB bus protocol vhdl i2c DB-I2C-M-APB complete I2C specifications verilog program for 16 bit processor verilog ARC processor i2c/APB to I2C interface
    Text: Digital Blocks DB-I2C-M-APB Semiconductor IP APB Bus I2C Controller General Description The Digital Blocks DB-I2C-M-APB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC, or other high performance microprocessor via the AMBA 2.0 APB System Interconnect Fabric to an I2C Bus. The I2C is a two-wire bidirectional interface


    Original     		PDF

    atmel h020

    Abstract: atmel h022 uart baud rate spear AA13 ARM926EJ-S MAC110 PBGA420 SPEAR-09-H022 Atmel ARM9 ATMEL 0905
    Text: SPEAR-09-H022 SPEAr Head ARM 926, 200K customizable eASIC™ gates, large IP portfolio SoC PRELIMINARY DATA Features • ARM926EJ-S - fMAX 266 MHz, 32 KI - 16 KD cache, 8 KI - KD tcm, ETM9 and JTAG interfaces ■ 200K customizable equivalent ASIC gates


    Original     		PDF SPEAR-09-H022 ARM926EJ-S PBGA420 atmel h020 atmel h022 uart baud rate spear AA13 MAC110 PBGA420 SPEAR-09-H022 Atmel ARM9 ATMEL 0905

    atmel h020

    Abstract: M25Pxxx state machine for ahb to apb bridge multiport memory controller A13 cristal ARM926EJ-S electrical ATMEL 0905 INPUT/atmel h020
    Text: SPEAr-09-H020 SPEAr Head ARM 926, 200K customizable eASIC™ gates, large IP portfolio SoC PRELIMINARY DATA Features • ARM926EJ-S - fMAX 266 MHz, 32 KI - 16 KD cache, 8 KI - KD tcm, ETM9 and JTAG interfaces ■ 200K customizable equivalent ASIC gates with


    Original     		PDF SPEAr-09-H020 ARM926EJ-S atmel h020 M25Pxxx state machine for ahb to apb bridge multiport memory controller A13 cristal ARM926EJ-S electrical ATMEL 0905 INPUT/atmel h020

    ahb to i2c

    Abstract: multiport memory controller
    Text: SPEAr ARM 946, 400K Gates e-ASIC, Large IP Portfolio SoC DATA BRIEF Features • ARM946-ES fMAX = 192MHz ■ 400k equivalent customizable gates ■ AMBA 2.0 compliant Bus fMAX = 96 MHz ■ Clock generator ■ SDRAM, SRAM / FLASH interfaces ■ Ethernet 10/100


    Original     		PDF ARM946-ES 192MHz PBGA568 35x35mm) 35x35 CD00061363 ahb to i2c multiport memory controller

    APB to I2C interface

    Abstract: spi controller with apb interface AMBA AHB DMA vhdl code for ddr sdram controller with AHB interface AMBA APB spi Cypress FX2 design of dma controller using vhdl ITU656 ahb to i2c SIMPLE VGA GRAPHIC CONTROLLER
    Text: LCD-Pro IP LCD-Pro IP modules DS0031 v1.01 – 20 July 2009 Datasheet: Table 1: Core Facts Implementation data Documentation Datasheet, User’s Manual Design File Formats EDIF netlist Constraint Files LPF file Reference Designs & Implementation examples


    Original     		PDF DS0031 APB to I2C interface spi controller with apb interface AMBA AHB DMA vhdl code for ddr sdram controller with AHB interface AMBA APB spi Cypress FX2 design of dma controller using vhdl ITU656 ahb to i2c SIMPLE VGA GRAPHIC CONTROLLER

    atmel h020

    Abstract: atmel h022 atmel 0713 0x16000000 Atmel PART DATE CODE AA13 ARM926EJ-S MAC110 PBGA420 SPEAR-09-H022
    Text: SPEAR-09-H022 SPEAr Head200 ARM 926, 200K customizable eASIC™ gates, large IP portfolio SoC Features • ARM926EJ-S - fMAX 266 MHz, 32 KI - 16 KD cache, 8 KI - KD TCM, ETM9 and JTAG interfaces ■ 200K customizable equivalent ASIC gates 16K LUT equivalent with 8 channels internal


    Original     		PDF SPEAR-09-H022 Head200 ARM926EJ-S 16-bit atmel h020 atmel h022 atmel 0713 0x16000000 Atmel PART DATE CODE AA13 MAC110 PBGA420 SPEAR-09-H022

    atmel h020

    Abstract: atmel 0713 ATMEL 620 spear linux uart baud rate spear AA13 ARM926EJ-S MAC110 PBGA420 SPEAR-09-H022
    Text: SPEAR-09-H022 SPEAr Head200 ARM 926, 200K customizable eASIC™ gates, large IP portfolio SoC PRELIMINARY DATA Features • ARM926EJ-S - fMAX 266 MHz, 32 KI - 16 KD cache, 8 KI - KD TCM, ETM9 and JTAG interfaces ■ 200K customizable equivalent ASIC gates


    Original     		PDF SPEAR-09-H022 Head200 ARM926EJ-S PBGA420 atmel h020 atmel 0713 ATMEL 620 spear linux uart baud rate spear AA13 MAC110 PBGA420 SPEAR-09-H022

    atmel h020

    Abstract: atmel 0713 AA13 ARM926EJ-S MAC110 PBGA420 SPEAR-09-H022 usb 3 sm Flash drive controller M25Pxxx state machine for ahb to apb bridge
    Text: SPEAR-09-H022 SPEAr Head200 ARM 926, 200K customizable eASIC™ gates, large IP portfolio SoC PRELIMINARY DATA Features • ARM926EJ-S - fMAX 266 MHz, 32 KI - 16 KD cache, 8 KI - KD TCM, ETM9 and JTAG interfaces ■ 200K customizable equivalent ASIC gates


    Original     		PDF SPEAR-09-H022 Head200 ARM926EJ-S PBGA420 atmel h020 atmel 0713 AA13 MAC110 PBGA420 SPEAR-09-H022 usb 3 sm Flash drive controller M25Pxxx state machine for ahb to apb bridge

    Untitled

    Abstract: No abstract text available
    Text: SPEAR-09-H022 SPEAr Head ARM 926, 200K customizable eASIC™ gates, large IP portfolio SoC DATA BRIEF Features • ARM926EJ-S - fMAX 266 MHz, 32 KI - 16 KD cache, 8 KI - KD tcm, ETM9 and JTAG interfaces ■ 200K customizable equivalent ASIC gates 16K LUT equivalent with 8 channels internal


    Original     		PDF SPEAR-09-H022 ARM926EJ-S PBGA420

    verilog code for eeprom i2c controller

    Abstract: verilog code for implementation of eeprom verilog code for i2c ,vhdl code for implementation of eeprom FPGA with i2c eeprom verilog code for uart apb tera term M24512-WMN6TP eeprom PROGRAMMING tutorial pmbus verilog
    Text: Application Note AC345 SmartFusion: Accessing EEPROM Using I2C Table of Contents Introduction . . . . . . . . . . . . . . . Design Example Overview . . . . . . . Description of the Design Example . . . Interface Description . . . . . . . . . . Software Implementation . . . . . . . .


    Original     		PDF AC345 verilog code for eeprom i2c controller verilog code for implementation of eeprom verilog code for i2c ,vhdl code for implementation of eeprom FPGA with i2c eeprom verilog code for uart apb tera term M24512-WMN6TP eeprom PROGRAMMING tutorial pmbus verilog

    i2c controller with apb interface

    Abstract: APB to I2C interface port expander 32-bit i2c CDC16xxF Can controllers can controller with apb interface
    Text: DEVELOPMENT TOOLS Complementary Tools for 16/32-Bit CAN Controllers April/2005 Complementary Tools for 16/32-Bit CAN Controllers For evaluation and early SW development, a set of extension boards is available. The boards have a standard interface and can be used in combination with the Application


    Original     		PDF 16/32-Bit April/2005 16xxF 32xxG. 32xxG 6255-001-1DT D-79108 D-79008 i2c controller with apb interface APB to I2C interface port expander 32-bit i2c CDC16xxF Can controllers can controller with apb interface

    PMO13701

    Abstract: ritdisplay 96x16 ritdisplay 96x16 SSD0300 oled display 96x16 96x16 oled i2c oled UNSIGNED SERIAL DIVIDER using vhdl OLED circuit details
    Text: Application Note AC347 SmartFusion: Interfacing with OLED using I2C Table of Contents Introduction . . . . . . . . . . . . . . Design Example Overview . . . . . . Description of the Design Example . . Interface Description . . . . . . . . . Software Implementation . . . . . . .


    Original     		PDF AC347 PMO13701 ritdisplay 96x16 ritdisplay 96x16 SSD0300 oled display 96x16 96x16 oled i2c oled UNSIGNED SERIAL DIVIDER using vhdl OLED circuit details

    ARM926EJ-S Implementation Guide

    Abstract: ARM926EJ-S verilog coding for APB bridge state machine for ahb to apb bridge 8 pin AHB ARM926E-JS verilog code for amba ahb master AMBA 2.0 AHB to APB BUS Bridge verilog code AMBA AHB to APB BUS Bridge verilog code ARM926EJ-S jtag
    Text: DATASHEET 0.11 µm Processor System for ARM926EJ-S cw001200_agflxr_2_0 February 2005 Preliminary DB08-000261-01 This document is preliminary. As such, it contains data derived from functional simulations and performance estimates. LSI Logic has not verified either the


    Original     		PDF ARM926EJ-STM cw001200 DB08-000261-01 cw001124 ARM926EJ-S Implementation Guide ARM926EJ-S verilog coding for APB bridge state machine for ahb to apb bridge 8 pin AHB ARM926E-JS verilog code for amba ahb master AMBA 2.0 AHB to APB BUS Bridge verilog code AMBA AHB to APB BUS Bridge verilog code ARM926EJ-S jtag

    GM16C450

    Abstract: GM16550 scr tic 106 16C550 ARM720T GDC21D601 GDC601 16550 initialization timing diagram of DMA Transfer
    Text: GDC21D601 32-Bit RISC MCU Ver 1.6 HDS-GDC21D601-9908 / 10 GDC21D601 The information contained herein is subject to change without notice. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by Hyundai for any infringements of patents or other rights of the third parties


    Original     		PDF GDC21D601 32-Bit HDS-GDC21D601-9908 0xFFFFFA00 0xFFFFFA04 0xFFFFFA08 0xFFFFFA10 0xFFFFFA14 0xFFFFFB00 GM16C450 GM16550 scr tic 106 16C550 ARM720T GDC21D601 GDC601 16550 initialization timing diagram of DMA Transfer

    LPC2300

    Abstract: VICvectCntl0-15 ARM7TDMI-S bsdl vic lpc2378 LPC2400 AN10576 LPC2378 8084 microcontroller arm7 bsdl LPC2378 Timer application notes
    Text: AN10576 Migrating to the LPC2300/2400 family Rev. 01 — 1 February 2007 Application note Document information Info Content Keywords LPC2000, LPC23xx, LPC24xx, Migration Abstract This application note covers the important features that were added to the LPC23xx/24xx family of devices. These features should be considered if


    Original     		PDF AN10576 LPC2300/2400 LPC2000, LPC23xx, LPC24xx, LPC23xx/24xx LPC210x/LPC22xx/LPC21xx LPC2300/LPC2400 AN10576 LPC2300 VICvectCntl0-15 ARM7TDMI-S bsdl vic lpc2378 LPC2400 LPC2378 8084 microcontroller arm7 bsdl LPC2378 Timer application notes

    MSC7110

    Abstract: SC1000 SC1400
    Text: Freescale Semiconductor Product Brief MSC7110PB Rev. 2, 12/2005 MSC7110 Low-Cost 16-Bit DSP with DDR Controller DMA 32 ch JTAG Port JTAG ASM2 AMDMA 128 Boot ROM (8 KB) 64 to IPBus Instruction Cache (16 KB) Extended Core Interface AMIC 128 AMEC 64 Multiplexer


    Original     		PDF MSC7110PB MSC7110 16-Bit SC1400 HDI16) HDI16 RS-232 MSC7110 SC1400 SC1000

    M2S050-1FG484I

    Abstract: M2s010-fgg484 axi interface ddr3 memory controller M2S050-FG484 M2S050T-1FG484I M2S120T-1FC1152I SECDED M2S005-VF400 M2S010T-FGG484 M2S050T-FG896
    Text: Product Brief SmartFusion2 System-on-Chip FPGAs Microsemi’s SmartFusion 2 SoC FPGAs integrate fourth generation flash-based FPGA fabric, an ARM® Cortex -M3 processor, and high performance communications interfaces on a single chip. The SmartFusion2 family is the industry’s lowest power, most


    Original     		PDF 51700115PB-5/2 M2S050-1FG484I M2s010-fgg484 axi interface ddr3 memory controller M2S050-FG484 M2S050T-1FG484I M2S120T-1FC1152I SECDED M2S005-VF400 M2S010T-FGG484 M2S050T-FG896

    STA2062A

    Abstract: LFBGA361 vic-16 ARM926 ARM926EJ 16x16x1.4 FIFO 32x8 i2c controller with apb interface APB to I2C interface STA2062
    Text: STA2062A Cartesio family infotainment application processor with embedded GPS Data Brief Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High performance ARM926 MCU up to 333 MHz MCU memory organization – Cache: 16 Kbyte instruction, 16 Kbyte data


    Original     		PDF STA2062A ARM926 64-channel 16-vectorized STA2062A LFBGA361 vic-16 ARM926EJ 16x16x1.4 FIFO 32x8 i2c controller with apb interface APB to I2C interface STA2062

    STA2062

    Abstract: STa2062 ARM926 LFBGA361 cartesio LFBGA36 ST OTG controller vic-16 ARM926 ARM926EJ ARM processor .4mm pitch
    Text: STA2062 Cartesio Infotainment application processor with embedded GPS Data Brief Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High performance ARM926 MCU up to 333MHz MCU memory organization – Cache: 16KByte instruction, 16KByte data


    Original     		PDF STA2062 ARM926 333MHz) 16KByte 32KByte 64KByte 512Byte 16bit 166MHz, STA2062 STa2062 ARM926 LFBGA361 cartesio LFBGA36 ST OTG controller vic-16 ARM926EJ ARM processor .4mm pitch

    LFBGA361

    Abstract: ST OTG controller APB to I2C interface VIC-16 ARM926 ARM926EJ STA2062 i2c controller with apb interface Reed-Solomon Decoder nand fifo
    Text: STA2062 Cartesio family Infotainment application processor with embedded GPS Data Brief Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High performance ARM926 MCU up to 333 MHz MCU memory organization – Cache: 16 KByte instruction, 16 KByte data


    Original     		PDF STA2062 ARM926 64-channel 16-vectorized LFBGA361 ST OTG controller APB to I2C interface VIC-16 ARM926EJ STA2062 i2c controller with apb interface Reed-Solomon Decoder nand fifo

    Untitled

    Abstract: No abstract text available
    Text: STA2062 Cartesio family Infotainment application processor with embedded GPS Data Brief Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High performance ARM926 MCU up to 333 MHz MCU memory organization – Cache: 16 KByte instruction, 16 KByte data


    Original     		PDF STA2062 ARM926

    Untitled

    Abstract: No abstract text available
    Text: SPEAR-09-H020 SPEAr Head ARM 926, 200K customizable eASIC™ gates, large IP portfolio SoC DATA BRIEF Features • ARM926EJ-S - fMAX 266 MHz, 32 KI - 16 KD cache, 8 KI - KD tcm, ETM9 and JTAG interfaces ■ 200K customizable equivalent ASIC gates with 8 channels internal DMA high speed


    Original     		PDF SPEAR-09-H020 ARM926EJ-S PBGA420

    virtex5 vhdl code for dvi controller

    Abstract: displayport implementation using verilog AMBA APB bus protocol vhdl code for spartan 6 audio HDMI verilog code DS735 LogiCORE IP DisplayPortTM v1.3 APB to I2C interface ModelSim 6.5c UG366
    Text: LogiCORE IP DisplayPort v1.3 DS735 July 23, 2010 Product Specification Introduction LogiCORE IP Facts The Xilinx LogiCORE™ IP DisplayPort™ interconnect protocol is designed for transmission and reception of serial-digital video at two standard rates of 1.62 Gbps


    Original     		PDF DS735 virtex5 vhdl code for dvi controller displayport implementation using verilog AMBA APB bus protocol vhdl code for spartan 6 audio HDMI verilog code LogiCORE IP DisplayPortTM v1.3 APB to I2C interface ModelSim 6.5c UG366

    Untitled

    Abstract: No abstract text available
    Text: Features • Atmel Voice CODEC - Digitizes and Encodes Speech Signals from the Microphone - Transforms into Analog Format Speech Signals for the Speaker - Based on State-of-the-Art Analog-to-Digital Conversion Techniques - Direct Interface to Off-Chip DSP for Com pression/Decom pression and Treatment


    OCR Scan     		PDF 32-bit 16-bit