IB20 Search Results

15ASTOP

Abstract: HM100
Contextual Info: HITACHI/ LOGIC/ARRAYS/MEM S'lE D • 4M=ib203 OOlbbb'l 3 ■ H M 1 0 0 5 0 4 F - 1 0 / 1 2 — Preliminary 65536-Words x 4-Bit Fully Decoded Random A ccess Memory ■ PIN A R R A N G EM EN T ■ DE SC R IPTIO N The HM100504 is E C L 100K compatible, 65536-words by 4-bits

Contextual Info: IB20-36 Series - Interchangeable Base Date: 8/31/10 Wall Plug-In, Switch Mode Power Supply RoHS Compliant, CEC Efficiency Level IV Rev: 083110 Page: 1 of 2 Features: • • • • • • • • • Universal Input 100 – 240 VAC 5 VDC to 35 VDC 20 to 36 Watts

IB204

Abstract: IB206 1401-14 IB202
Contextual Info: IB202 IB204 IB206 TRIAC .8 Amp. RMS, Plastic TO-92 600V FEATURES: • Forward Current: ,8A R M S • Voltage Ratings: to 600V • High Surge Current: 8A • Gate Sensitivity: 2mA Typical, 1st & 3rd Quad • Hard Glass Passivated Junction • Economical TO-92 Package

2sk298

Abstract: 2SK299 3tb 40 Hitachi Scans-001
Contextual Info: 44<ib205 G013024 blE D IHIT4 4bT 2SK298,2SK299 HITACHI/C OPTOELECTRONICS SILICON N-CHANNEL MOS FET HIGH SPEED POWER SW ITCHING , HIGH FREQUENCY POWER AMPLIFIER • FEATURES • Low On-Resistance. • High Speed Switching. • High Cutoff Frequency. • No Secondary Breakdown.

2SK1199

Abstract: ir2a Hitachi Scans-001 ir2a diode diode ir2a
Contextual Info: 2SK1199 44<ib20S GG13EaT 6D3 « H I T 4 HITACHI/ OPTOELECTRONICS blE D S IL IC O N N -C H A N N E L M O S FET HIGH SPEED POWER SWITCHING • FEATURES • Low On-Resistance • High Speed Switching • Low Drive Current • • No Secondary Breakdown Suitable for Switching Regulator and

K685

Abstract: 2SK685 ED44
Contextual Info: bl E D 44<ib205 2SK685 0 0 1 3 1 2 e] • HITM HITACHI/ OPTOELECTRONICS SILICON N-CHANNEL MOS FET HIGH SPEED POWER SWITCHING ■ FEATURES • Low On-Resistance • High Speed Switching • Low Drive Current 1. Gale 2. Drain (Flange) 3. Source ( Dimensions i

A63A

Abstract: 74LSOO
Contextual Info: •Quadruple 2-input Positive AND Gates with Open Collector Outputs IP IN ARRANGEMENT ¡C IR C U IT S C H E M A T IC ^ ) •RECOM M ENDED OPERATING CONDITIONS Symbol min typ max High level output voltage Item VOH - - 5.5 Unit V Low level output current IOL

DIVIDE-BY-256

Abstract: ONU block diagram 74LSOO HD74LS393 a63a
Contextual Info: •D u a l 4-bit Binary Counters This circuit contains eight master-slave flip-flops and ad­ ditional gating to implement tw o individual four-bit counters. The HD74LS393 comprises tw o independent four-bit binary counters each having a clear and a clock input.

74LSOO

Abstract: HD74LS490
Contextual Info: HD74LS490. This c irc u it d itio n a l contains gating to eigh t master-slave im p le m e n t tw o Dual 4 -b it Decade Counters flip -flo p s ind ividu al 4 -b it and ad ­ I BLOCK DIAGRAM K decade counters. Each decade c o u n te r has ind ividu al clo ck, clear, and

74LSOO

Abstract: HD74LS642 Hitachi Scans-001
Contextual Info: ♦ O c ta l Bus Transceivers inverted open-collector outputs This octal bus transceiver is designed fo r asynchronous two-way communication between data buses. The devices transmit data from the A bus to the B bus or from the B bus to the A bus de­ pending upon the level at the direction control (D IR ) input. The

74LSOO

Contextual Info: •Quadruple 2-input Positive NAND Gates with Open Collector Outputs •C IR C U IT S C H E M A T IC ^ ) BPIN ARRANGEMENT ■RECOMMENDED OPERATING CONDITIONS Symbol min typ max High level output voltage y oh - - 5 .5 Low level output c u rre n t IO L - -

74LSOO

Abstract: CI 2210 HD74LSoop
Contextual Info: •T rip le 3-input Positive NOR Gates • C IR C U IT S C H E M A T IC ^ B P IN ARRANGEMENT ■ELECTRICAL CHARACTERISTICS ( Ta= - 2 0 - +75°C ) Item S ym bol T e s t C o n d itio n s min typ* m ax V lH 2 .0 - - V lL - - 0 .8 U n it Input v o lta g e V

74LSOO

Abstract: 1S2074
Contextual Info: •Q u a d ru p le 2-input Positive N AND Schmitt-triggers •C IR C U IT S C H EM A TIC ^ HPIN ARRANGEMENT ■ELECTRICAL CHARACTERISTICS ( Ta= - 20- + 75”C ) Item Symbol min typ* max Unit Vt + V cc — 5V T e s t Conditions 1.4 1.6 1.9 V Vt ~ V cc — 5V

74LSOO

Abstract: HD74LS367A kl66
Contextual Info: HD74LS367A * Hex Bus Drivers non-inverted data outputs with three-state outputs I PIN ARRANGEMENT I CIRCUIT SCHEMATIC D r i v e r se c tio n (1 / 6 ) C o n t r o l se c tio n Ootpu Control Ci ~ï7 ]vVcc — 1Output Cont roi Ci 'vLLKy L jc t-E I 6 " Y r]D *

HD74LSoop

Abstract: 1S2074 74LSOO HD74LS195A Hitachi Scans-001 Scans-0014928
Contextual Info: H D 74 L S 19 5A . 4-b¡t Parallel-Access Shift Registers This 4-bit register features parallel inputs, parallel outputs. is loaded into the associated flip-flop and appears at the out­ puts after the positive transition of the clock input. During loading, serial data flow is inhibited. Shifting is accomplished

Contextual Info: •Quadruple 2-input High-voltage Interface Positive NAND Gates • C IR C U IT SC H EM A TIC O ^ B P IN ARRANGEMENT ■RECOM M ENDED OPERATING CONDITIONS Item S ym bol High lev e l o u tp u t v o lta g e Voh L ow lev el o u tp u t c u r r e n t min ty p

Contextual Info: •D u a l 4-input Positive AND Gates •PIN ARRANGEMENT ICIRCUIT SCHEMATICO^ ■ELECTRICAL CHARACTERISTICS Item Input voltage O utput voltage Symbol VlH VlL VOH V>L I ih It L ¡1 Input c u rren t S h o rt-c irc u it output c u rren t Supply c u rren t Input clam p voltage

Contextual Info: ADE-207-122 Z HD49319F CMOS 9-Bit A/D Converter Preliminary Rev. 0 Nov. 1993 HITACHI Description Features The H D 49319F is a h igh -sp eed , low -pow er monolithic CMOS 9-bit A/D converter LSI. • • • • Resolution: 9 bits Double +5.0 V / +3.3 V power supply (Digital

Contextual Info: HE8813VG GaAIAs IRED Description The HE8813VG is a 880 nm band GaAIAs infrared light emitting diode with a double heterojunction struc­ ture. It is suitable as a light source for still camera autofocus mechanisms. Features Package Type HE8813VG: VG • High efficiency and high power output

74LSOO

Abstract: HD74LS374 HD74LSoop
Contextual Info: HD74LS374 • O c t a l D-type Edge-triggered Flip-Flops with th ree-state IP IN ARRANGEM ENT The H D74LS374, 8-bit registers features totem-pole threestate outputs designed specifically for driving highly-capacitive or relatively iow-impedance loads. The high-impedance third

1S2074

Abstract: 74LSOO HD74LS75 Hitachi Scans-001
Contextual Info: •Q uad ru ple Bistable Latches The H D 74LS75 is ideally suited for use as temporary storage for binary information between processing units and input/ • P IN ARRANGEMENT output or indicator units. Information present at a data D input is transferred to the Q output when the enable (G) is

HD74LS154

Abstract: 74LSOO ir 2210 ic LS2074
Contextual Info: •4-line-to-16-line Decoders/Demultiplexers This decoder utilizes T T L circuitry to decode four binarycoded inputs into one of sixteen mutually exclusive outputs when both the strobe inputs, G1 and G2, are low. The demul­ tiplexing function is performed by using the 4 input lines to

HD74LSoop

Abstract: 74LSOO 400M HD74LS54 Hitachi Scans-001
Contextual Info: •4 -w id e 2-input, 3-input AND-OR-INVERT Gates • C IR C U IT SCHEM ATIC B P IN ARRANGEMENT N ote The schem atic w ith in the dashed line is included the half inp ut term inals o f H D 7 4 L S 5 4 . ■ELECTRICAL CHARACTERISTICS T a = - 20- + 75°C )

74LSOOP

Abstract: 74LSOO
Contextual Info: HD74LS21 •D u al 4-input Positive AND Gates •PIN ARRANGEMENT ¡CIRCU IT SCHEMATICO^ ■ ELECTRICAL CH A RA CTERISTICS Item Symbol Input voltage VlL I6i IlH Input current IlL ¡1 Short-circuit output current Supply current Input clamp voltage * T est Conditions