IC UC66 Search Results

IC UC66 Result Highlights (5)

Part	Manufacturer	Description
SCL3400-D01-004	Murata Manufacturing Co Ltd	2-axis (XY) digital inclinometer
SCC433T-K03-PCB	Murata Manufacturing Co Ltd	2-Axis Gyro, 3-axis Accelerometer combination sensor on Evaluation Board
D1U54T-M-2500-12-HB4C	Murata Manufacturing Co Ltd	2.5KW 54MM AC/DC 12V WITH 12VDC STBY BACK TO FRONT AIR
SCC433T-K03-10	Murata Manufacturing Co Ltd	2-Axis Gyro, 3-axis Accelerometer combination sensor
SCC433T-K03-004	Murata Manufacturing Co Ltd	2-Axis Gyro, 3-axis Accelerometer combination sensor

IC UC66 Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
ulc xc3030 Abstract: ic UC66 CPLD EPM 7128 XC3030A-5PL84C Contextual Info: T em ic UC Series_ Matra MHS Universal Logic Circuits Description The UC series of ULC s is w ell suited for converting medium- to large-sized CPLDs and FPGAs. D evices are implemented in high-performance CMOS technology with 0.85-mm drawn channel lengths, and are capable	OCR Scan	85-mm 300-mil 150-mil ulc xc3030 ic UC66 CPLD EPM 7128 XC3030A-5PL84C	PDF
UD10 Abstract: UD09 UD27 matra universal logic circuit Contextual Info: T e m ic UD Series Matra M H S Universal Logic Circuits Description The U D series of U L C ^ s is optimized for conversion of small- to medium-sized PLDs, CPLDs and FPGAs. This series use a unique architecture that provides a high I/O-to-gate ratio. Devices are implemented in	OCR Scan		PDF

Catalog Datasheet

Type

Document Tags

PDF

ulc xc3030

Abstract: ic UC66 CPLD EPM 7128 XC3030A-5PL84C
Contextual Info: T em ic UC Series_ Matra MHS Universal Logic Circuits Description The UC series of ULC s is w ell suited for converting medium- to large-sized CPLDs and FPGAs. D evices are implemented in high-performance CMOS technology with 0.85-mm drawn channel lengths, and are capable

OCR Scan

85-mm 300-mil 150-mil ulc xc3030 ic UC66 CPLD EPM 7128 XC3030A-5PL84C

PDF

UD10

Abstract: UD09 UD27 matra universal logic circuit
Contextual Info: T e m ic UD Series Matra M H S Universal Logic Circuits Description The U D series of U L C ^ s is optimized for conversion of small- to medium-sized PLDs, CPLDs and FPGAs. This series use a unique architecture that provides a high I/O-to-gate ratio. Devices are implemented in

OCR Scan

PDF