ID02 Search Results

Contextual Info: 传感器|上海闰安工业传感器有限公司 页码 1/1 电感式接近开关 标准外型尺寸mm 产品序列号 ID02 标准距离Sn(mm) 具 NPN 常开 ID02-BNZ1 NPN 常闭 ID02-ANZ1 NPN 常开+常闭 ID02-BANZ1 DC PNP 常开 ID02-BPZ1 型 PNP 常闭

ARM11

Abstract: ARM926EJ-S 0529C
Contextual Info: ARM Compiler toolchain Version 4.1 Introducing the ARM Compiler toolchain Copyright 2010-2011 ARM. All rights reserved. ARM DUI 0529C ID020411 ARM Compiler toolchain Introducing the ARM Compiler toolchain Copyright © 2010-2011 ARM. All rights reserved.

lm814

Abstract: ID32-001
Contextual Info: TOSHIBA TC59LM814/06BFT-22,-24,-30 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 4,194,304-WORDSX4BANKSX16-BITS DOUBLE DATA RATE FAST CYCLE RAM 8,388,608-WORDSX4BANKSX8-BITS DOUBLE DATA RATE FAST CYCLE RAM DESCRIPTION TC59LM814/06BFT are a CMOS Double Data Rate Fast Cycle Random Access Memory DDR

MSM7581

Abstract: PAD10 PAD31 NC-641 M7581
Contextual Info: O K I Semiconductor MSM7581_ ITU-T G.721 4ch ADPCM TRANSCODER G E N E R A L D ESC R IP T IO N The MSM7581 is an A D PC M tran sc o d er w h ich is u se d b y th e n ew dig ital cordless system . It converts 64 k b p s voice PCM serial d a ta to 32 k b p s ITU-T G.721 A D PC M serial d ata, a n d vice

Contextual Info: STM32F328x8 ARM -Cortex®-M4 32b MCU+FPU, 64KB Flash, 16KB SRAM, 2 ADCs, 3 DAC channels, 3 COMPs, Op-Amp, 1.8 V Datasheet −production data Features • Core: ARM®-32-bit-Cortex®-M4 CPU with FPU 72 MHz max , single-cycle multiplication and HW division, and DSP instruction

Contextual Info: IME D INTEGRATED DEVICE • 4Ö2S771 0003^22 1 ■ 16-BIT CMOS ERROR DETECTION AND CORRECTION UNIT MICROSLICE PRODUCT FEATURES: • • ■ T -¥ £ -/7 Pin-compatible to all versions of the 2960 • Military product available compliant to MIL-STD-883, Class B

M66507

Abstract: 66P507 MARK A03 MSM66507 41BW-10
Contextual Info: O K I Semiconductor MSM66507/66P507 OLM S-66K Series 16-Bit Microcontroller GENERAL DESCRIPTION The M SM66507/66P507 is a high-performance 16-bit microcontroller that employs OKI original nX-8/500 CPU core. The MSM66507/66P50 7 includes a 16-bit CPU, ROM, RAM, a 10-bit A /D converter, serial ports,

inverter circuit diagram toshiba a100

Abstract: str 6856 "spindle motor" DP8473 IEEE1284 N82077 PC87338 PC97 PC97338 PD765A
Contextual Info: PC87338/PC97338 ACPI 1.0 and PC97 Compliant SuperI/O General Description Differences between the PC87338 and PC97338 are indicated in italics. These differences are summarized in Appendix A. The PC97338 is a fully ACPI 1.0 and PC97 compliant, ISA based Super I/O. It is functionally compatible with

DS33R41

Abstract: DS21455 DS21458 DS2155 DS33Z41
Contextual Info: DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers www.maxim-ic.com GENERAL DESCRIPTION FEATURES 10/100 IEEE 802.3 Ethernet MAC MII and RMII Half/Full Duplex with Automatic Flow Control The DS33R41 extends a 10/100 Ethernet LAN

Contextual Info: GEC P L E S S E Y MAY 1997 M 1 O !\ I l f I () K S PRELIMINARY INFORMATION DS4575 -1.5 VP5311B/VP5511B NTSC/PAL DIGITAL VIDEO ENCODER (supersedes edition in October 1996 Media 1C Hanbook, HB4599-1.0) The VP5311/VP5511 converts digital Y, Cr, Cb, data into analog NTSC/PAL composite video and S-video signals.

Contextual Info: WMGEC piessey PRELIM IN ARY INFORMATION DS4516- 1.1 VP551D NTSC/PAL DIGITAL VIDEO ENCODER The VP551 converts digital Y, Cr, Cb, data into analog NTSC/PAL com posite video and S-video signals The outputs are capable of driving doubly term inated 75 ohm loads with standard video levels.

mc6808

Abstract: mc3870 6818A 1N4148 CDP6805E2 CDP6818A MC6800 CDP6805E
Contextual Info: QDP6818A 33 H a r r is CMOS Real-Time Clock With RAM Features Description • • • • • • The C D P6818A Real-Tim e C lock plus RAM is a peripheral device w hich includes the unique MOTEL concept fo r use w ith various m icroprocessors, m icrocom puters and larger

Contextual Info: ag GEC PLESSEY MAY1995 P R E L IM IN A R Y IN F O R M A T IO N S E M I C O N D U C T O R S DS402S- 1.7 VP531 NTSC/PAL DIGITAL VIDEO ENCODER The VP531 converts digital Y, Cr, Cb, data into analog NTSC/PAL composite video and S-video signals The outputs are capable of driving doubly terminated 75 ohm

Contextual Info: SEPTEMBER 1995 PRELIMINARY INFORMATION DS4028 - 2.0 VP531 NTSC/PAL DIGITAL VIDEO ENCODER The VP531 converts digital Y, Cr, Cb, data into analog NTSC/PAL composite video and S-video signals The outputs are capable of driving doubly terminated 75 ohm loads with standard video levels.

DS26521

Abstract: BTS 308 EC17 pinout of bel 187 transistor rspc 193 ec5 BBC FTL 3-2 G.SHDSL Industry Single-Chip DS2155 DS2156
Contextual Info: DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS33R11 extends a 10/100 Ethernet LAN segment by encapsulating MAC frames in HDLC or X.86 LAPS for transmission over a T1/E1/J1 data stream. §

CW1260

Abstract: CW1250
Contextual Info: BAL-CW1250D3 Balun transformer with integrate matching Datasheet  production data Description STMicroelectronics BAL-CW1250D3 is a balun balanced/unbalanced device designed to transform a single ended signal to differential signals in WLAN application.This

HY57V161610B

Contextual Info: C » « Y U H D f t P - - - - - - - - - - • H Y 57V 161610B 2 Banks x S12K X 16 Bit Synchronous DRAM DESCRIPTION The Hyundai HY57V161610B is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V161610B is organized as 2banks of

circuit in GPR

Abstract: 2W2C L18411
Contextual Info: S3CB018/FB018 8 INSTRUCTION SET INSTRUCTION SET OVERVIEW GLOSSARY This chapter describes the CalmRISC instruction set and the details of each instruction are listed in alphabetical order. The following notations are used for the description. Table 8-1. Instruction Notation Conventions

Contextual Info: intei M2118 FAMILY 16,384 x 1 BIT DYNAMIC RAM M IL IT A R Y M2118-4 120 270 320 Maximum Access Time ns Read, Write Cycle (ns) Read-Modify Cycle (ns) • Single +5V Supply, ±10% Tolerance M2118-7 150 320 410 ■ RAS Only Refresh ■ HMOS Technology ■ Low Power: 150 mW Max. Operating

G6003

Contextual Info: DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers www.maxim-ic.com GENERAL DESCRIPTION FEATURES 10/100 IEEE 802.3 Ethernet MAC MII and RMII Half/Full Duplex with Automatic Flow Control The DS33R41 extends a 10/100 Ethernet LAN

pt-041

Abstract: DC028
Contextual Info: DS33Z11 Ethernet Mapper www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS33Z11 extends a 10/100 Ethernet LAN segment by encapsulating MAC frames in HDLC or X.86 LAPS for transmission over a PDH/TDM data stream. The serial link supports bidirectionalsynchronous interconnect up to 52Mbps over xDSL,

Contextual Info: Ordering num ber: EN4359A _ No. 4359A II CMOS LS LC7472T, LC74721M On-screen Video Display Controllers S d ü V O for NTSC or PAL-M Overview The LC74721 and LC74721M are CMOS, video display controllers for superimposing text and low-level graph­

STM CL-80

Abstract: P87C591VFA 8xC591 80C51 P83C591 P83C591VFA P83C591VFB P87C554 P87C591 P87C591VFB
Contextual Info: INTEGRATED CIRCUITS DATA SHEET P8xC591 Single-chip 8-bit microcontroller with CAN controller Preliminary Specification File under Integrated Circuits, IC28 2000 Jul 26 Philips Semiconductors Preliminary Specification Single-chip 8-bit microcontroller with CAN controller

AL2A smd

Abstract: D17012GF AE3A mPD1720 car tuner 14x20 SMD NL AL2A d17012gf nec japan DIODE ku 1490 transistor SMD DK -RN LED display for radio
Contextual Info: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT uPD17012GF-056 PLL FREQUENCY SYNTHESIZER AND CONTROLLER FOR FM/MW/LW TUNER AUTOMOBILE APPLICATIONS The /iPD17012GF-056 is a CMOS LSI chip designed for use in FM/MW/LW tuners utilizing a PLL frequency synthesizer design for worldwide applications.