INTEL 85C508 Search Results

85C508

Abstract: 28-PIN CERDIP
Contextual Info: SUPPORT COMPONENTS INTEL CORPORATION 85C508 High Address Decoder • ■ ■ ■ ■ High-Speed Address Decode For High-Performance Designs Wide Address Decode – 16 Inputs Up to 8 Chip-Select Outputs Low-Power CHMOS Technology Total Propagation Delay of 7.5 nsec

Intel 85C508

Abstract: Intel AP-346 AP-346 29208* intel
Contextual Info: in U APPLICATION NOTE r a ilO M O N IM tf AP-346 November 1990 Am 29000*/2 7960CX Burst EPROM Interface INTEL PROGRAMMABLE MEMORY OPERATION *Am29000 is a trademark o Advanced Micro Devices, Inc. Order Number: 292081-001 5-260 29000/27960CX BURST EPROM INTERFACE

intel PLD

Contextual Info: INTEL CORP UP/PRPHLS . • i n t g MME D ■ - . MÔSbl75 0101313 5 I ■ ITLl ' p ftg y o m M ? l " P i - 6 - 1^ - 27960CX PIPELINED BURST ACCESS 1M (128K x 8) CHMOS EPROM Pipelined Addressing fo r Optimal Bus Bandwidth on 80960CA — N ext Addressing Overlaps Last Data

85C508

Abstract: Intel 85C508 290175 incir
Contextual Info: i n t o l. 85C508 FAST 1-MICRON CHMOS DECODER/LATCH juPLD • High-Performance Programmable Logic Device for High-Speed Microprocessorto-Memory Decode ■ 16 Dedicated Inputs for Address/Data Bus Decoding; 8 Latched Outputs; 1 Global Latch Enable ■ Supports Intel386 , i468TM, ¡860tm,

5AC312

Abstract: LIN VHDL source code 3 bit carry select adder verilog codes carry save adder verilog program 8 bit carry select adder verilog codes vhdl code for carry select adder 5AC324 verilog code for fixed point adder PLCC68 PLCC84
Contextual Info: FLEXlogic Device Kit Manual FLEXlogic Device Kit Manual 981-0405-001 September 1994 090-0610-001 Data I/O has made every attempt to ensure that the information in this document is accurate and complete. Data I/O assumes no liability for errors, or for any incidental,

85C508

Abstract: Intel IPLDview-286 290134 290175 n85c508 5097
Contextual Info: in t e i 85C508/85C509 FAST 1-MICRON CHMOS DECODER/LATCH juPLDs High-Performance Programmable Logic Device for High-Speed Microprocessorto-Memory Decode: — 85C508: Active-Low Outputs — 85C509: Active-High Outputs Extremely High Speed— tpp 7.5 ns max , 133.3 MHz (max), t£o 4.5 ns

atmel 93c66

Abstract: PH29EE010 2764 EEPROM 537RU10 sst ph29ee010 556RT7A 556RT5 intel 8755 eprom 2716 537RU17
Contextual Info: Универсал ьны й програм матор Sterh ST­011 Производст во: Россия. Цен а: 17500 руб. с НД С. ST­011 имеет всего одну универсальную DIP­42 панель для программирования

7 segment display using 8086

Abstract: intel 82230 80287XL 80C88A
Contextual Info: my* NAME:. _ _ _ :_ •l^A M COMPANY: -wf, ADDRESS: CITY: f ZIP: STATE: COUNTRY: PHONE NO.: Chi 'H'-'- ORDER NO. YV TITLE TTTTT" r r n n .i i t i 1 1 T l 1" ! i QTY. PRICE i X - X . 1 1 1 1 I I I

T3I marking code

Abstract: 27960CX 80960CA 85C508 N27960CX Marking code varc 29023
Contextual Info: intei 27960CX PIPELINED BURST ACCESS 1M 128K x 8 CHMOS EPROM Synchronous 4 Byte Data Burst Access No Glue Interface to 80960CA High Performance Clock to Data Out — Zero Wait State Data to Data Burst — Up to 33 MHz 80960CA Performance Asynch Microcontroller Reset Function

27960CX

Abstract: 80960CA 85C508 N27960CX 3A353
Contextual Info: intei 27960CX PIPELINED BURST ACCESS 1M 128K x 8 CHMOS EPROM Synchronous 4 Byte Data Burst Access No Glue Interface to 80960CA High Performance Clock to Data Out — Zero Wait State Data to Data Burst — Up to 33 MHz 80960CA Performance Asynch Microcontroller Reset Function

cl-001

Abstract: 85C508 Intel 85C508 80960CA 27960CX intel PLD
Contextual Info: IP ^ iy M O G M V intei 27960CX PIPELINED BURST ACCESS 1M 128K x 8 CHMOS EPROM Pipelined Addressing for Optimal Bus Bandwidth on 80960CA — Next Addressing Overlaps Last Data Byte CHMOS Ill-E for High Performance and Low Power — 125 mA Active, 30 mA Standby

led 7 segment LDS 5161 AK

Abstract: led 7 segment LDS 5161 AH 7-segment 4 digit LFD 5522 AKO 701 434 tdso 5160 k lds 7 segment LDS 5161 AK led 7 segment LDS 5161 As manual LG VARIABLE FREQUENCY DRIVE is3 -20/led 7 segment LDS 5161 AH ako 544 126
Contextual Info: NAM E; C O M P A N Y :. ADDRESS; . . C IT Y ; S TA TE: Z IP : C O U N T R Y :. P H O N E N O .; . .I — ;.-,. ' - V- ORDER NO. QTY. TITLE fTTT ±j . • . n i i lU . . II 11 1 i i 1111 1-T 2 .-.

Contextual Info: 85C960 1-MICRON CHMOS 80960 K-SERIES BUS CONTROL juPLD • Burst Logic, Ready Control, and Address Decode Support for 80960 KA/KB Embedded Controllers in Single Chip ■ Operates with 80960KA/KB at 20 MHz and 25 MHz ■ Ice = 50 mA Max. ■ UV Erasable CerDIP or OTPTM

ICE-50

Abstract: 290134 290192
Contextual Info: in t e T 85C960 1-MICRON CHMOS 80960 K-SERIES BUS CONTROL juPLD • Operates with 80960KA/KB at 20 MHz and 25 MHz ■ Ice ~ 50 mA Max. ■ UV Erasable CerDIP or OTPtm ■ 100% Generlcally Testable Logic Array ■ Based on Low Power CHMOS HIE* Technology

29023

Abstract: VXXXX 5204 eprom
Contextual Info: in te i 27960CX PIPELINED BURST ACCESS 1M 128K x 8 CHMOS EPROM Synchronous 4 Byte Data Burst Access Pipelined Addressing for Optimal Bus Bandwidth on 80960CA — Next Addressing Overlaps Last Data Byte No Glue Interface to 80960CA High Performance Clock to Data Out

d85c960-25

Abstract: UP200 85C508 D85C960-20
Contextual Info: in t ô l, 85C960 1-MICRON CHMOS 80960 K-SERIES BUS CONTROL jaPLD • ■ ■ ■ B u rst L ogic, R e a d y C o n tro l, and A d d re s s D e c o d e S u p p o rt fo r 80 96 0 K A /K B E m b e d d e d C o n tro lle rs in Single Chip ■ O p e ra te s w ith 8 0 9 6 0 K A /K B a t 20 M H z

29023

Contextual Info: ln¥ I A E W M 1 ! DMIF@®IM]ATrO@M 27960CX PIPELINED BURST ACCESS 1M 128K x 8 EPROM Synchronous 4 Byte Data Burst Access Pipelined Addressing for Optimal Bus Bandwidth on 80960CA — Next Addressing Overlaps Last Data Byte No Glue Interface to 80960CA

29023

Contextual Info: in te i 27960CX PIPELINED BURST ACCESS 1M 128K x 8 CHMOS EPROM • S yn ch ro n o u s 4 B yte D a ta B u rst A c c e s s ■ ■ No G lue In te rfa c e to 8 0 96 0C A ■ High P e rfo rm a n c e C lo ck to D ata O u t — Z e ro W ait S ta te D a ta to D ata B u rst