INTERLAKEN NETWORK PROCESSOR Search Results

ARM11 processor block diagram

Abstract: ARM11 processor NFP-3240
Contextual Info: SiNFP-32xx Flow Processor: Ruggedized Netronome NFP; 133 MHz DDR3 Product Highlights • Source-code compatibility including backwards-compatibility with Intel IXP28XX microengines for customer application migration • High-performance solution with low power consumption for a broad

HX300

Abstract: Xelerated marvell ethernet switch IEEE1588 integrated mac and phy
Contextual Info: Marvell Xelerated HX300 Family of Network Processors 100 Gbps - 160 Gbps NPUs with Integrated Traffic Manager, Switch, Programmable Pipeline and Ethernet MACs PRODUCT OVERVIEW The Marvell Xelerated® HX300 family of network processors NPUs are leading Carrier Ethernet packet processing devices

CS6051

Abstract: MAC+120G
Contextual Info: Product Brief CS605x Family of Transport Processors Key Features         Product Overview Transport and mapping of 100G, 40G, and 10G signals for OTN and Ethernet networks Aggregation & de-aggregation of up to ten 10GE/ODU2 e , and two 40GE/

interlaken network processor

Abstract: OC-768 10G serdes bert overhead processor Cortina Systems
Contextual Info: TM Product Brief Cortina Systems CS1999 40G SONET/SDH Framer and POS Mapper Overview 40G POS Mapper is connected to the receive and transmit ports of the System Interface. The Cortina Systems® CS1999 OC-768 SONET Framer/ Mapper CS1999 Framer Application Specific Standard

88E6097

Abstract: 88E6020 88E1119 88E6071 Marvell 88E1512 88AP270M 88W8897 Marvell PHY 88E6352 88PG867 MV64460
Contextual Info: 2015 Marvell Product Selector Guide TOTAL SOLUTIONS FROM MARVELL Providing a b ro a d s p e c t r u m o f s o l u t i o n s a c ro ss a w i d e ra n g e o f m a r ke t s e g m e n t s . TABLE OF CONTENTS Application Processors .

Contextual Info: TM Product Brief Cortina Systems CS1999 40G SONET/SDH Framer and POS Mapper Overview 40G POS Mapper is connected to the receiv e and transmit ports of the S ystem Interface. The Cortina Systems® CS1999 OC-768 SONET Framer/ Mapper CS1999 Framer Application Specific Standard

tcam

Abstract: ternary content addressable memory 100GbE Altera Stratix V datasheets of optical fpgas 100g phy interlaken network processor receiver ber fec 100G 40GBASE-R 10Gbase-kr transmitter
Contextual Info: Addressing 100-GbE Line-Card Design Challenges on 28-nm FPGAs WP-01128-1.1 White Paper As various standard bodies finalize their 100G standards for transport, Ethernet, and optical interfaces, FPGAs play a vital role for early adopters of technology who want

Marvell 88E1512

Abstract: 88E6352 88E6176 Marvell 88E1510 88E6172 88E6071 88E6020 88E6161 88E6097 88w8782
Contextual Info: 2012 Marvell Product Selector Guide TOTAL SOLUTIONS FROM MARVELL Providing a b ro a d s p e c t r u m o f s o l u t i o n s a c ro ss a w i d e ra n g e o f m a r ke t s e g m e n t s . TABLE OF CONTENTS Application Processors .

Achronix Semiconductor

Contextual Info: I Speedster22i HD FPGA Family DS004 Rev. 2.6 – May 8, 2014 Preliminary Highlights • • • Advanced highest-density and highest‐bandwidth FPGA • Over 1.7 million effective look‐up‐tables • Abundant embedded hard IP for communica‐

Contextual Info: Freescale Semiconductor Product Brief Document Number:T4240PB Rev 0, 06/2013 T4240 Product Brief Also supports T4160 Contents 1 Introduction 1 The T4240 QorIQ multicore processor combines 12 dualthreaded e6500 Power Architecture processor cores for a

Contextual Info: Marvell Xelerated AX300/AX200 Family of Programmable Ethernet Switches With Integrated Programmable Switching, Traffic Management and Ethernet MACs PRODUCT OVERVIEW The Marvell Xelerated® AX300/AX200 family of programmable Ethernet switches represents a new generation of devices

EZchip

Abstract: EZchip NP3 EZchip NP4 QSGMII tcam 45X45 Hamilton 2077930 interlaken network processor NP-4 Ezchip
Contextual Info: EZchip Technologies NP-4 100-Gigabit Network Processor for Carrier Ethernet Applications Product Brief Features „ Single-chip, programmable, 100-Gigabit throughput 50-Gigabit full duplex wire-speed network processor „ Line card, services card, pizza box and switch card

Prestera

Contextual Info: Marvell Prestera 98EX3316 Advanced Multi-layer High-Capacity Packet Processor for Enterprise, Data Center, and Metro Ethernet PRODUCT OVERVIEW The Marvell Prestera® 98EX3316 packet processors deliver multi-layer Gigabit Ethernet GbE , 10GbE, 40GbE, and

Achronix Semiconductor

Abstract: ACX-KIT-HD1000-100G
Contextual Info: PRODUCT BRIEF HD1000 Development Kit HD1000 DEV KIT HIGHLIGHTS Development Board Features • HD1000 22-nm FPGA see below for FPGA details • CFP cage for 100GE line interface –– Adaptable to 2x40GE or 10x10GE • Interlaken interface (AirMax connector pair)

Prestera 98DX4251

Abstract: Prestera DX Networking 98DX4251 Marvell prestera dx marvell Prestera Prestera
Contextual Info: Marvell Prestera 98DX4251 Next-generation Packet Processor for Service Delivery Applications PRODUCT OVERVIEW The Marvell Prestera® DX family of packet processors enables high-density 10GbE/1GbE solutions in service provider and campus applications. Prestera 98DX4251 is the eighth-generation Prestera DX product that enables line-rate packet processing with a mix

100GBASE-R

Abstract: QSFP 40G transceiver 40GBASE-R CPRI multi rate gearbox pcie gen3 QSFP optical active cable QSFP M20K 5SGX
Contextual Info: Stratix V Device Family Overview SV51001-1.3 This document provides an overview of the Stratix V device features. Many of these features are enabled in the Quartus ® II software version 10.0. The remaining features will be enabled in future versions of the Quartus II software.

HF35-F1152

Abstract: KF40-F1517 5sgxa3 eye-q 400 NF40-F1517 interlaken gf35 NF45 KF35-F1152
Contextual Info: Stratix V Device Family Overview January 2011 SV51001-1.6 SV51001-1.6 This document provides an overview of the Stratix V devices and their features. Many of these devices and features are enabled in the Quartus ® II software version 10.1. The remaining devices and features will be enabled in future versions of the

b 103g

Abstract: interlaken ternary content addressable memory WP-01127-1 computer networking diagram Double high-speed switching diode optical switch fabric interlaken network processor tcam Altera Stratix V
Contextual Info: Integrating 100-GbE Switching Solutions on 28-nm FPGAs WP-01127-1.1 White Paper With high-speed 100-GbE communication network standards converging, switching functions play a key role in the smooth functioning of the Internet. The aggregated network traffic doubles every six months and grows in complexity as it is transported

Contextual Info: MegaCore IP Library Release Notes MegaCore IP Library Release Notes 101 Innovation Drive San Jose, CA 95134 www.altera.com RN-IP-13.1 Feedback 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos

Contextual Info: Altera Transceiver PHY IP Core User Guide Subscribe Feedback UG-01080 2013.7.1 101 Innovation Drive San Jose, CA 95134 www.altera.com TOC-2 Contents Introduction to the Protocol-Specific and Native Transceiver PHYs.1-1 Protocol-Specific Transceiver

BCM88750

Abstract: BCM56840 BCM5684 BCM88650 BCM88030 BCM56640 bcm5664 10G-PON 40GbE NetLogic
Contextual Info: Broadcom B CM8 86 50 S e ries World Most Dense 100GbE Swi tc h i n g S o lut io n 200G INTEGRATED PACKET PROCESSOR, TRAFFIC MANAGER, AND FABRIC INTERFACE SINGLE-CHIP DEVICE Overview Highlights • Highly scalable, field-proven DUNE architecture Traffic Manager, with deep packet buffers

adaptive algorithm dpd

Abstract: virtex GTH xilinx digital Pre-distortion DSP48E1 SX475T FPGA Virtex 6 Ethernet Virtex 6 3G-SDI serializer 6.25G interlaken network processor
Contextual Info: FPGA FAMILY virtex-6 FPGAs Th e H ig h-Pe r for mance Prog ram mab le Si licon Fou n dation for Targ ete d Desig n Platfor ms Satisfying the Insatiable Demand for Higher Bandwidth The Programmable Imperative The High-Performance Silicon Foundation • Competitive forces are driving

QSFP28 I2C

Contextual Info: Arria 10 Device Overview 2013.09.04 AIB-01023 Subscribe Feedback Altera’s Arria FPGAs and SoCs deliver optimal performance and power efficiency in the midrange. By using TSMC's 20-nm process technology on a high-performance architecture, Arria 10 FPGAs and SoCs

Contextual Info: ACX-KIT-HD1000-100G Development Kit User Guide UG034, March 11, 2014 UG034, March 11, 2014 1 Copyright Info Copyright 2014 Achronix Semiconductor Corporation. All rights reserved. Achronix is a trademark and Speedster is a registered trademark of Achronix Semiconductor Corporation.