IR TSOP 557 Search Results

Contextual Info: fax id: 1075 CY7C1020V _ 3 2 K x 16 Static RAM BLE is LOW, then data from I/O pins (l/O-j through l/0 8), is written into the location specified on the address pins (A0 through A 14). If byte high enable (BHE) is LOW, then data from I/O pins (l/0 9 through l/O i6) is written into the location speci­

MT28F400B1

Abstract: MAX714
Contextual Info: PRELIMINARY |M |^ E S m V I MT28F004B1/MT28F400B1 ET 4 MEG FLASH MEMORY I FLASH MEMORY 4 MEG S m artV o ltag e, BOOT BLOCK, EXTENDED TEMPERATURE FEATURES PIN ASSIGNMENT Top View • Extended temperature range operation: -40° to +85° C • Seven erase blocks:

sharp laser diodes

Abstract: TSOP855
Contextual Info: VISHAY INTERTECHNO L O G Y , INC . INTERACTIVE data book ir receiver modules vishay semiconductors vse-db0090-1010 Notes: 1. To navigate: a Click on the Vishay logo on any datasheet to go to the Contents page for that section. Click on the Vishay logo on any Contents

Contextual Info: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT juPD42S18165L, 4218165L 3.3 V OPERATION 16 M BIT DYNAMIC RAM 1 M-WORD BY 16-BIT, HYPER PAGE MODE, BYTE READ/WRITE MODE Description The ftPD42S18165L, 4218165L are 1 048 576 words by 16 bits CMOS dynamic RAMs with optional hyper page

70241k

Abstract: d5611 61c256 ic 9022 61c64 RELIABILITY REPORT ISSI vacuum tubes CMS 2015 S/TRANSISTOR J 5804 EQUIVALENT 28F010P
Contextual Info: ISSI Integrated Silicon Solution, Inc. Quality and Reliability 1997-1998 An ISO 9001 Company ISSI ® Reliability Report 1997-1998 An ISO 9001 Company 1997 Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. • 2231 Lawson Lane • Santa Clara, CA 95054

c9013

Abstract: 84 pin PBGA oscilloscope MTBF TSMC retention memory dc 8069 IS61C1024 IC Data-book Q-16 car radio 14x20 TSOP 8638
Contextual Info: ISSI Integrated Silicon Solution, Inc. Quality and Reliability 1997-1998 An ISO 9001 Company ISSI ® Quality System Manual QUALITY Reliabilty Report 1997-1998 RELIABILITY Integrated Silicon Solution, Inc. An ISO 9001 Company 1997 Integrated Silicon Solution, Inc.

Contextual Info: a Advanced Micro Devices Am27X256 256 Kilobit 32,768 x 8-Bit CMOS ExpressROM Device DISTINCTIVE CHARACTERISTICS • As an OTP EPROM alternative: — Factory optimized programming — Fully tested and guaranteed ■ As a Mask ROM alternative: — Shorter leadtime

Contextual Info: i n y 4-MBIT 256K x 16, 512K x 8 SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY 28F400BV-T/B, 28F400CV-T/B, 28F004BV-T/B, 28F400CE-T/B, 28F004BE-T/B • Intel SmartVoltage Technology — 5V or 12V Program/Erase — 2.7V, 3.3V or 5V Read Operation — Increased Programming Throughput

WT16LD

Abstract: tc 97101 INTERNAL DIAGRAM OF IC 7476
Contextual Info: PRELIMINARY M IC n a iM 1 M T 16LD T 164(S), M T16LD(T)464(X)(S) 1 MEG, 4 MEG X 64 DRAM M OD ULES 1 MEG, 4 MEG x 64 DRAM MODULE 8, 32 MEGABYTE, 3.3V, OPTIONAL SELF REFRESH, FAST PAGE OR EDO PAGE MODE FEATURES • JEDEC- and industry-standard pinout in a 168-pin,

F160B3TA

Contextual Info: PRELIMINARY SMART 3 ADVANCED BOOT BLOCK 4-, 8-, 16-, 32-MBIT FLASH MEMORY FAMILY 28F400B3, 28F800B3, 28F160B3, 28F320B3 28F008B3, 28F016B3, 28F032B3 n Flexible SmartVoltage Technology — 2.7 V-3.6 V Read/Program/Erase — 12 V V p p Fast Production Programming

TCS 5513

Abstract: MX28F2100TTC
Contextual Info: i\/!X2BF21 OOT 2M-BITC256K x 8 / 1 2 8 K x 1 6 CMOS FLASH MEMORY FEATURES • 262,144x8/131,072x16 switchable • Fast access time: 70/90/120ns • Low power consumption - 50mA maximum active current - lOOnAmaximum standby current • Programming and erasing voltage 12V + 7%

Contextual Info: in tj 2-MBIT 128K x 16, 256K x 8 BOOT BLOCK FLASH MEMORY FAMILY 28F200BX-T/B, 28F002BX-T/B • x8/x16 Input/Output Architecture — 28F200BX-T, 28F200BX-B — For High Performance and High Integration 16-bit and 32-bit CPUs ■ x8-only Input/Output Architecture

574 nec

Abstract: ft 4a
Contextual Info: DATA SHEET NEC / MOS INTEGRATED CIRCUIT ¿¿P D 4 2 1 8 0 5 1 M-BIT DYNAMIC RAM 128K-WORD BY 8-BIT, HYPER PAGE MODE EDO Description The ¿¿PD421805 is a 131,072 words by 8 bits CMOS dynamic RAM with optional hyper page mode (EDO). Hyper page mode (EDO) is a kind of the page mode and is useful for the read operation.

29057

Abstract: intel 4269
Contextual Info: 28F002BC 2-MBIT 256K X 8 BOOT BLOCK FLASH MEMORY • High Performance Read — 80/120 ns Max. Access Time 40 ns Max. Output Enable Time a Low Power Consumption — 20 mA Typical Read Current ■ x8-Only Input/Output Architecture — Space-Constrained 8-bit

nec A2C

Contextual Info: DATA SHEET NEC MOS INTEGRATED CIRCUIT _ ¿ ¿ P P 421165 1 M-BIT DYNAMIC RAM 64K-WORD BY 16-BIT, HYPER PAGE MODE EDO , BYTE READ/WRITE MODE Description The ¿¿PD421165 is a 65,536 words by 16 bits CMOS dynamic RAM with optional hyper page mode (EDO).

nec A2C

Abstract: kmxx nec vt 575
Contextual Info: DATA SHEET NEC MOS INTEGRATED CIRCUIT _ / ¿ P D 4 2 1 1 6 5 1 M-BIT DYNAMIC RAM 64K-WORD BY 16-BIT, HYPER PAGE MODE EDO , BYTE READ/WRITE MODE D escription The î î PD421165 is a 65,536 words by 16 bits CMOS dynamic RAM with optional hyper page mode (EDO).

active suspension

Abstract: m56v16 m56v1640010
Contextual Info: O K I Semiconductor MSM56V16400 2-Bank x 2,097,152-Word x 4-Bit SYNCHRONOUS DYNAMIC RAM DESCRIPTION The MSM56V16400 is a 2-bank x 2,097,152-w ord x 4-bit synchronous dynam ic RAM, fabricated in OKI's CMOS silicon gate process technology. The device operates at 3.3 V. The inputs and

Contextual Info: FUJITSU SEMICONDUCTOR DATA SHEET DS05-20824-2E FLASH MEMORY CMOS 4 M 5 1 2 K X 8 MBM29LV004T/MBM29LV004B • FEATURES • Single 3.0 V read, program, and erase Minimizes system level power requirements • Compatible with JEDEC-standard commands * * * •

Contextual Info: K M 4 4 C 4 10 4 B S CMOS DRAM ELECTRONICS 4M x 4 Bit CMOS Dynamic RAM with Extended Data Out DESCRIPTION This is a family of 4,194,304 x 4 bit Extended Data Out CMOS DRAMs. Extended Data Out Mode offers high speed random access of memory cells within the same row, so called Hyper Page Mode. Power

Contextual Info: SAMSUNG ELECTRONICS INC b4E » • 7^4142 0013381 KM48C512LL bO S ■ SMÓK CMOS DRAM 5 12K x8 Bit CMOS Dynamic RAM with Fast Page Mode FEATURES GENERAL DESCRIPTION • Performance range: The Samsung KM48C512LL is a CMOS high speed 524,288 bit x 8 Dynamic Random Access Memory. Its

ic tl 0741

Abstract: UPD 552 C
Contextual Info: NEC MOS INTEGRATED CIRCUIT ¿¿PD42S4210A, 424210A 4 M-BIT DYNAMIC RAM 256 K-WORD BY 16-BIT, HYPER PAGE MODE, BYTE READ/WRITE MODE Description The /JPD42S4210A. 424210A are 262 144 w ords by 16 bits dynamic CMOS RAMs w ith optional hyper page mode. Hyper page mode is a kind o f the page mode and is useful fo r the read operation.

HT27LC020

Contextual Info: HT27LC020 CMOS 256K´8-Bit OTP EPROM Features • Operating voltage: +3.3V · 256K´8-bit organization · Programming voltage · Fast read access time: 90ns - VPP=12.5V±0.2V - VCC=6.0V±0.2V · Fast programming algorithm · Programming time 75ms typ. · High-reliability CMOS technology

HT27LC040

Contextual Info: HT27LC040 CMOS 512K´8-Bit OTP EPROM Features • Operating voltage: +3.3V · 512K´8-bits organization · Programming voltage - VPP=12.5V±0.2V · Fast read access time: 90ns · Fast programming algorithm - VCC=6.0V±0.2V · Programming time 75ms typ. · High-reliability CMOS technology

42-10A

Contextual Info: NEC MOS INTEGRATED CIRCUIT ju P D 4 2 S 4 2 1 0 A , 4 2 4 2 1 0 A 4 M BIT DYNAMIC RAM 256 K-WORD BY 16-BIT, HYPER PAGE MODE, BYTE READ/WRITE MODE Description ThepPD 42S4210A , 424210 A are 262 144 w ords by 16 bits dynam ic CMOS RAMs w ith optional hyper page