IR7* IRC Search Results

radiation hardened cpu

Abstract: 82C59A HS-80C85RH HS-80C86RH HS-82C59ARH
Contextual Info: H S-82C 59A R H ¡D h a rris Radiation Hardened CMOS Programmable Interrupt Controller PREVIEW Pino u t Features c s tz 1 28 □ vcc W RC 2 27 □ A0 RDC 3 26 □ ÎHTÀ d7 c 4 25 13 IR7 06 C 5 24 3 I R 6 05 C 6 23 □ IR5 04 C 7 22 □ IR4 03 C 6 21 13 IR3

3D marking

Abstract: marking CJD P11M
Contextual Info: AD 0 0 REWStO TO? CC 0512-0213-05 t EE1 A OF rI ir7.i h t t t h A A 1 } I J— I ijl 1— 1 I ; t 1— 1 l i t 1 t l . l I— I lU I— 1 1 j t 1 nri m ry i m nri m nr: rwn n n nn ts E iX i i n Qp QC ŒD tS iiju-o» j DP RW cZ3 un Ä 3 D f 3 D O t 3 i S J t X J C 2 D a c a K J X i i X 3 i a ì tap ix i O D CSD CXJ O C O C O C O D CK) CjD

block diagram of intel 8259 pic

Abstract: block diagram 8259A operation word diagram 8259A intel 8259 interfacing 8259A to the 8086 pic 8259 MCS-80 8259A mcs-60 MCS-85
Contextual Info: in te i p k h il d im id iïm iy 8 2 5 9 A /8 2 5 9 A -2 /8 2 5 9 A -8 PROGRAMMABLE INTERRUPT CONTROLLER IAPX 86, IAPX 88 Compatible • Programmable Interrupt Modes MCS-80 , MCS-85® Compatible ■ Individual Request Mask Capability Eight-Level Priority Controller

82C59A harris

Abstract: I82C59A 8086 hex code
Contextual Info: S3HARRIS 82C59A S E MI C O N D U C T O R REFERENCE APP NOTE 109 CMOS Priority Interrupt Controller February 1992 Features Description • 12.5MHz, 8MHz and 5MHz Versions Available - 12.5MHz Operation. 82C59A-12 - 8MHz

8085 WORD DOC

Abstract: m82c59 82C59A harris I82C59A 82C59A 8086 microprocessor hex code
Contextual Info: HARRIS S E M C O N D S E C T O R IS t f j 43QS271 DQllOOl 1 J ” ~ ^ & - 3 3 '/ 3 S 3 h a r r is Q 2 C 5 9 A CMOS Priority a . . Ä Interrupt Controller R E F E R E N C E P A G E 4 -1 5 6 F O R a p p l ic a t io n n o t e 109 Features Pinouts TOP VIEW • Pin Compatible with NMOS 8259A

cd 3313 eo

Abstract: I82C59A M82C59A 82C59A harris
Contextual Info: H A RR IS S E M I C O N D S E C T O R 82C59A MfciE D 4302271 GD3Ô750 1 H A R R IS S E M I C O N D U C T O R IHAS • P 5 Z -3 3 -I3 REFERENCE APP NOTE 109 CMOS Priority Interrupt Controller February 1992 Features Description • 12.5MHz, 8MHz and 5MHz Versions Available

MCS-85

Contextual Info: in iß l M8259A PROGRAMMABLE INTERRUPT CONTROLLER Military • ■ ■ ■ 8086, 8088, 80186 Compatible MCS -85 Compatible Eight-Level Priority Controller Expandable to 64 Levels ■ ■ ■ ■ Programmable Interrupt Modes Individual Request Mask Capability

Contextual Info: fU h a rris U U S2C5QA S E M I C O N D U C T O R REFERENCE APP NOTE 109 CMOS Priority Interrupt Controller February 1992 Features Description • 12.5MHz, 8MHz and 5MHz Versions Available The Harris 82C59A is a high performance CMOS Priority Interrupt Controller manufactured using an advanced 2

Contextual Info: 82C 59A /883 h a r r is june 1989 CM O S Priority Interrupt Controller Pinouts F eatures • This Circuit is Processed in Accordance to M il-S td -8 8 3 C and is Fully Conform ant U nder the Provisions of Paragraph 1.2.1. • Com patible with NMOS 8259A • 8M Hz and 5M Hz Versions Available

m82c59a

Contextual Info: h a r r i s Q 2 C 5 9 A CM OS Priority R E F E R E N C E P A G E 4 -15 6 F O R , application note 109 . a i. Pinouts Features • • • • • • • • • • • • • x y* Interrupt Controller Pin Compatible with NMOS 8259A 8MHz and SMHz Versions Available

Contextual Info: HARRIS SENICOND S E CT OR 33 HARRIS IbE D • 43 052 71 Q 0 1 4 T 4 0 S ■ 82C 59A /883 T ^ r a - 3 3 - i 3 CMOS Priority Interrupt Controller June 1989 P ino u ts F eatures 8 2 C 5 9 A /8 8 3 C ER A M IC DIP • This Circuit is Processed in Accordance to MII-Std-883C and is Fully

B259A

Abstract: 2132AF B259A-2 tv csc
Contextual Info: in te i 8259A / 8259A -2/ 8259A-8 PROGRAMMABLE INTERRUPT CONTROLLER • iAPX 86, iAPX 88 Compatible ■ Individual Request Mask Capability ■ MCS-80 , MCS-85® Compatible ■ Single + 5V Supply No Clocks ■ Eight-Level Priority Controller ■ 28-Pin Dual-ln-Line Package

block diagram 8259A

Abstract: um8259
Contextual Info: U M C U M 8 2 5 9 A -2 Programmable interrupt Controller ffü - Features • ■ iA P X 8 6 , iA P X 88 com patible ■ Eight-level p rio rity c o n tro lle r ■ Expandable to 64 levels ■ Programmable in te rru p t modes Individual request mask capability

MCS-80

Abstract: intel 8085 MCS intel 80C88 -harris -intersil 8086 interrupt structure 8086 opcode table for 8086 microprocessor cpu intel 8085 MCS-80/85 8085A-2 8259A-2 MCS-85
Contextual Info: U M 8 2 S 9 A - 2 Programmable Interrupt Controller S? Features • ¡APX86, ¡APX88 com patible ■ MCS-80 , MCS-85® com patible ■ Eight-level p r io rity co n tro lle r ■ Expandable to 64 levels ■ Programmable in terrupt modes ■ Individual request mask capability

microsequencer

Abstract: CORE i3 ARCHITECTURE MC68377 pipeline in core i3 IR 30 D1
Contextual Info: SECTION 2 CPU32X This document describes the modifications of the CPU32 to create the CPU32X. 2.1 Features The CPU32X is greater than two times faster at the same external clock rate than the CPU32 using similar speed memory devices. This performance improvement is

LT280A

Abstract: IR7* IRC
Contextual Info: Hall IC LT280A LT280A GaAs Hall IC for Noncontact Switch Unidirectional magnetic field-type I Features • Outline Dimensions Suitable for portable equipment due to 3V operation ● Operation by small magnet due to high sensitivity Operating point < 30mT

a5901

Contextual Info: FU JITSU NMOS PROGRAMMABLE INTERRUPT CONTROLLER July 1966 Edition 2.2 NMOS PROGRAMMABLE INTERRUPT CONTROLLER The M B L8259A Programmable Interup t C ontroller handles up to eight vectored p rio rity interrupts fo r the CPU. It is cascadable fo r up to 64 vectored p rio rity interrupts w ith o u t additional circu itry. I t is packaged in a 28-pin DIP, uses

8086 microcomputer

Abstract: 8086 interrupt structure interrupt structure of 8086 TMP8259AP 8086 structure interrupt 8086 8086 timing diagram MPU85
Contextual Info: TOSHIBA TMP8259AP TOSHIBA M OS TYPE DEGITAL INTEGRATED CIRCUIT Silicon M o n o lith ic N -C hann el Silicon G ate M O S TM P8259AP PR O G R A M M A B LE INTERRUPT CONTROLLER 1. GENERAL DESCRIPTION TMP8259AP is a programmable interrupt controller. It handles up to eight vectored

S4 59A

Abstract: m82c59a
Contextual Info: OKI semiconductor MSM82C59A-2RS/GS/JS PROGRAMMABLE INTERRUPT CONTROLER GENERAL DESCRIPTION The M SM 82C59A-2 is a programmable in te rru p t c o n tro lle r fo r use ¡n M S M 8 0C 8 5 A /A -2 and M SM 80C 86/88 m icroco m p ute r systems. Based on C M OS silicon gate te c h n o lo g y , th is device fe a tu re s an e x tre m e ly lo w s ta n d b y c u rre n t o f 1 0 0 ¿¿A

sab 8259a

Abstract: SAB8259A function of block 8259A 8086 interrupt structure 8259A block diagram 8259A SAB 8086
Contextual Info: SIEMENS SAB 8259A, SAB 8259A-2 Programmable Interrupt Controller • C om patible w ith SAB 8086/88, SAB 80186/188 and SAB 80286 processor fam ilies • Program m able interrupt modes • Individual request mask capability • • S in g le + 5 V supply no clocks

VL1935-13PC

Contextual Info: V L S I Tech nology , in c . VL1935 SYNCHRONOUS DATA LINE CONTROLLER FEATURES • HDLC, SDLC, ADCCP and CCITT X.25 Compatible • Global Address Recognition • SDLC Loop Data Link Capability • Extendable Control Field • Full or Half Duplex Operation • Automatic Zero Insertion and Deletion

RIO 1R0

Abstract: W2106
Contextual Info: OKI semiconductor MSM82C59A-2 RS/GS/JS PROGRAMMABLE INTERRUPT CONTROLLER GENERAL DESCRIPTION The M SM 82C59A-2 is a program mable in te rru p t c o n tro lle r fo r use in M S M 8 0C 8 5 A /A -2 and M SM 80C 86/88 m icroco m p ute r systems. Based on C M O S s ilico n g a te te c h n o lo g y , th is d e vice fe a tu re s an e x tre m e ly lo w s ta n d b y c u rre n t o f 1 0 0 pA

Contextual Info: MOTOROLA H S E M IC O N D U C TO R TECHNICAL DATA MC2672 Advance Inform ation Programmable Video Timing Controller PVTC The M C2672 p ro g ra m m a b le v id e o tim in g c o n tro lle r (PVTC) is a p ro g ra m m a b le device d esig n ed fo r use in CRT te rm in a ls and d isp la ys syste m s th a t e m p lo y ra ste r scan te c h n iq u e s . The PVTC g e n e r­

I8259A

Abstract: 8080 intel microprocessor pin diagram i8259 MCS-86 timing diagram of 8086 maximum mode intel 8288 8086 microprocessor max mode operation write cycle timing diagram of 8086 maximum mode MCS-80 8288 bus controller by intel
Contextual Info: PGanmiSfflDIMÀEIV I8259A PROGRAMMABLE INTERRUPT CONTROLLER INDUSTRIAL • iAPX 86 C om patible m Program m able Interrupt M odes ■ MCS-80 , 85® C om patible ■ Individual R equest Mask C apability ■ Eight-Level Priority Controller ■ Single + 5V Supply N o Clocks