JANUAIY1995 Search Results

HEF4043BT

Abstract: HEF4043B HEF4043BD HEF4043BP
Contextual Info: HEF4043B MSI V QUADRUPLE R/S LATCH WITH 3-STATE OUTPUTS The HEF4043B is a quadruple R/S latch w ith 3-state outputs w ith a common o u tp u t enable Input EO . Each latch has an active HIGH set in p u t (Sq to S3 ), an active HIGH reset in p u t (Rg to R3 ) and

V53C104D

Contextual Info: M O S E L V IT E U C V53C104D HIGH PERFORMANCE, LO W POWER 256K X 4 B IT FAS T PAG E MODE CMOS DYNAMIC RAM PRELIMINARY 60 HIGH PERFORMANCE V53C104D 70 80 Max. RAS Access Time, tRAC 60 ns 70 ns 80 ns Max. Column Address Access Time, 0CAA) 30 ns 35 ns 40 ns

Contextual Info: M O S EL V IT E L IC V53C 16258H 2 5 6 K X 16 P A G E M O D E C M O S D Y N A M IC R A M W ITH E X T E N D E D D A TA O U T P U T HIGH PERFORMANCE P R E LIM IN A R Y 45 50 55 60 Max. RAS Access Time, tRAc 45 ns 50 ns 55 ns 60 ns Max. Column Address Access Time, (tCAA)

Contextual Info: M O SEL V IT E U C V52C8126 MULTIPORT VIDEO RAM WITH 128K X 8 DRAM AND 256 X 8 SAM 70 80 10 1 r a c 70 ns 80 ns 100 ns Max. CAS Access Time, (tCAc) 20 ns 25 ns 25 ns Max. Column Address Access Time, ( t ^ ) 35 ns 40 ns 50 ns Min. Fast Page Mode Cycle Time, (tPC)

Contextual Info: M O SEL VETEUC V52C4256 MULTIPORT VIDEO RAM WITH 256K X 4 DRAM AND 512 X 4 SAM HIGH PERFORMANCE V52C4256 60 70 80 10 Max. RAS Access Time, tRAC 60 ns 70 ns 80 ns 100 ns Max. CAS Access Time, (tCAC) 15 ns 20 ns 25 ns 25 ns Max. Column Address Access Time, (1M )

Contextual Info: MOSEL VtTEU C PRELIMINARY V400J32/36 4M x 32 & 4M X 36 CMOS MEMORY MODULES Features Description • The V 400J32 M em ory M odule is organized as 4,194,304 x 32 bits and the V400J36 is orgranized as 4,194,304 x 36 bits in a 72-lead single-in-line m odule. T he 4M x 32 m em ory m odule uses 32 4M x

HEF4508BP

Abstract: HEF4015B HEF4019B HEF4508B HEF4508BD HEF4508BT sot94 d2b bus
Contextual Info: HEF4508B MSI DUAL 4-BIT LATCH The HEF4508B is a dual 4-bit latch, which consists of two identical independent 4-bit latches with separate strobe ST , master reset (MR), output-enable input (EO) and 3-state outputs (O). With the ST input in the HIGH state, the data on the D inputs appear at the corresponding outputs

Y7T77

Contextual Info: M OSEL VTTEUC P R E L IM IN A R Y V404J232 and V404J236 2M x 32 and 2M x 36 CMOS MEMORY MODULES Features Description • 2,097,152 x 32/36 bit organization ■ Utilizes 1M x 4 C M O S DRAMs ■ Fast access times: 70 ns, 80 ns ■ Fast Page mode operation ■ Low power dissipation

HEF4094BP

Abstract: HEF4094BT HEF4094BD HEF4094B
Contextual Info: HEF4094B MSI 8-STAGE SHIFT-AND-STORE BUS REGISTER The HEF4094B is an 8 -stage serial sh ift register having a storage latch associated w ith each stage fo r strobing data from the serial input to parallel buffered 3-state outputs Og to O 7 . The parallel outputs

HEF4046BP

Abstract: HEF4046B HEF4046BD HEF4046BT 7Z74624 HE4000B P10102 HEF4046B MSI HEF4046BPN
Contextual Info: HEF4046B M SI PHASE-LOCKED LOOP The HEF4046B is a phase-locked loop circuit that consists of a linear voltage controlled oscillator VCO and two different phase comparators with a common signal input amplifier and a common comparator input. A 7 V regulator (zener) diode is provided for supply voltage regulation if necessary.

V53C1OON

Contextual Info: M O S E L V IT E L IC V53C100N HIGH PERFORMANCE, 3.3 VOLT 1M X 1 BIT FAST PAGE MODE CMOS DYNAMIC RAM 60/60L 70/70L 80/80L 60 ns 70 ns 80 ns Max. Column Address Access Time, tCAA 35 ns 40 ns 45 ns Max. CAS Access Time, (tCAC) 20 ns 25 ns 25 ns Min. Fast Page Mode Cycle Time, (1p c )

HEF4510BT

Abstract: HEF4510BP
Contextual Info: HEF4510B MSI BCD UP/DOWN COUNTER The HEF4510B is an edge-triggered synchronous up/down BCD counter with a clock input CP , an up/down count control input (UP/DN), an active LOW count enable input (CE), an asynchronous active HIGH parallel load input (PL), four parallel inputs (Pg to P3), four parallel outputs (Oq to O3 ),

v52c4258

Contextual Info: M O S E L V IT E U C V52C4258 MULTIPORT VIDEO RAM WITH 256K X 4 DRAM AND 512X 4 SAM HIGH PERFORMANCE V52C4258 60 70 80 10 60 ns 70 ns 80 ns 100 ns Max. CAS Access Time, tcAc 15 ns 20 ns 25 ns 25 ns Max. Column Address Access Time, ( t^ ) 30 ns 35 ns 40 ns

Contextual Info: MOSEL VITELIC V52C8126 MULTIPORT VIDEO RAM WITH 128K X 8 DRAM AND 256 X 8 SAM HIGH PERFORM ANCE V52C8126 70 80 10 Max. RAS Access Time, tRAC 70 ns 80 ns 100 ns Max. CAS Access Time, (tCAC) 20 ns 25 ns 25 ns Max. Column Address Access Time, (tM ) 35 ns 40 ns