JEDEC DRAWING WQFN Search Results
JEDEC DRAWING WQFN Result Highlights (1)
| Part | ECAD Model | Manufacturer | Description | Download | Buy |
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JEDEC DDR5 temperature sensor with 0.5 °C accuracy 6-DSBGA -40 to 125 |
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JEDEC DRAWING WQFN Datasheets Context Search
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Contextual Info: To request a full data sheet, please send an email to: display_contact@list.ti.com. PACKAGE OPTION ADDENDUM 26 – October – 2012 PACKAGING INFORMATION Orderable Device Status 1 Pack Type Pack Drawing Pins Pack Qty TPS65632ARTER ACTIVE WQFN RTE 16 3000 |
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TPS65632ARTER TPS65632ARTET TPS65632AGRTET Level-2-260C-1 | |
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Contextual Info: To request a full data sheet, please send an email to: display_contact@list.ti.com. PACKAGE OPTION ADDENDUM www.ti.com 20-Jan-2011 PACKAGING INFORMATION Orderable Device TPS65168RSBR Status 1 ACTIVE Package Type Package Drawing WQFN RSB Pins Package Qty |
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20-Jan-2011 TPS65168RSBR Level-2-260C-1 | |
TPS65168RSBRContextual Info: To request a full data sheet, please send an email to: display_contact@list.ti.com. PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status 1 TPS65168RSBR ACTIVE Package Type Package Pins Package Drawing Qty WQFN RSB |
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11-Apr-2013 TPS65168RSBR Level-2-260C-1 | |
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Contextual Info: To request a full datasheet, please send an email to: idls_contact@list.ti.com PACKAGE OPTION ADDENDUM www.ti.com 6-May-2013 PACKAGING INFORMATION Orderable Device Status 1 TPS65640RHRR PREVIEW Package Type Package Pins Package Drawing Qty WQFN RHR 28 3000 |
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6-May-2013 TPS65640RHRR Level-2-260C-1 | |
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Contextual Info: LMK04820 Family Low-Noise Clock Jitter Cleaner with Dual Loop PLLs 1.0 General Description 3.0 Features The LMK04820 family is the industry's highest performance clock conditioner with JEDEC JESD204B support. The dual loop PLLatinum architecture enables sub-100 fs RMS jitter |
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LMK04820 JESD204B sub-100 | |
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Contextual Info: LMK04820 Family Low-Noise Clock Jitter Cleaner with Dual Loop PLLs 1.0 General Description 3.0 Features The LMK04820 family is the industry's highest performance clock conditioner with JEDEC JESD204B support. The dual loop PLLatinum architecture enables sub-100 fs RMS jitter |
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LMK04820 JESD204B sub-100 | |
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Contextual Info: TPA6132A2 www.ti.com . SLOS597 – DECEMBER 2008 25-mW DIRECTPATH STEREO HEADPHONE AMPLIFIER WITH POP SUPPRESSION |
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TPA6132A2 SLOS597 25-mW TPA6132) | |
AIWIContextual Info: TPA6132A2 www.ti.com . SLOS597 – DECEMBER 2008 25-mW DIRECTPATH STEREO HEADPHONE AMPLIFIER WITH POP SUPPRESSION |
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TPA6132A2 SLOS597 25-mW TPA6132) AIWI | |
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Contextual Info: LP2995 www.ti.com SNVS190L – MAY 2004 – REVISED JUNE 2012 LP2995 DDR Termination Regulator Check for Samples: LP2995 FEATURES 1 • • • • • • • 2 • Low output voltage offset Works with +5v, +3.3v and 2.5v rails Source and sink current Low external component count |
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LP2995 SNVS190L LP2995 LLP-16 | |
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Contextual Info: LMK04820 Family Low-Noise Clock Jitter Cleaner with Dual Loop PLLs 1.0 General Description 3.0 Features The LMK04820 family is the industry's highest performance clock conditioner with JEDEC JESD204B support. The dual loop PLLatinum architecture enables sub-100 fs RMS jitter |
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LMK04820 JESD204B sub-100 | |
TLV320AIC3104
Abstract: TLV320AIC33 TPA6132 TPA6132A2 TPA6132A2RTER TPA6132A2RTET
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TPA6132A2 SLOS597 25-mW TLV320AIC3104 TLV320AIC33 TPA6132 TPA6132A2 TPA6132A2RTER TPA6132A2RTET | |
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Contextual Info: TPA6132A2 www.ti.com . SLOS597 – DECEMBER 2008 25-mW DIRECTPATH STEREO HEADPHONE AMPLIFIER WITH POP SUPPRESSION |
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TPA6132A2 SLOS597 25-mW | |
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Contextual Info: TPA6132A2 www.ti.com . SLOS597 – DECEMBER 2008 25-mW DIRECTPATH STEREO HEADPHONE AMPLIFIER WITH POP SUPPRESSION |
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TPA6132A2 SLOS597 25-mW TPA6132) | |
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Contextual Info: TPA6132A2 www.ti.com . SLOS597 – DECEMBER 2008 25-mW DIRECTPATH STEREO HEADPHONE AMPLIFIER WITH POP SUPPRESSION |
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TPA6132A2 SLOS597 25-mW TPA6132) | |
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Contextual Info: TPA6132A2 www.ti.com . SLOS597 – DECEMBER 2008 25-mW DIRECTPATH STEREO HEADPHONE AMPLIFIER WITH POP SUPPRESSION |
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TPA6132A2 SLOS597 25-mW TPA6132) | |
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Contextual Info: TPA6132A2 www.ti.com . SLOS597 – DECEMBER 2008 25-mW DIRECTPATH STEREO HEADPHONE AMPLIFIER WITH POP SUPPRESSION |
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TPA6132A2 SLOS597 25-mW | |
51C SOIC8Contextual Info: LP2995 www.ti.com SNVS190M – FEBRUARY 2002 – REVISED MARCH 2013 LP2995 DDR Termination Regulator Check for Samples: LP2995 FEATURES DESCRIPTION • • • • • • • The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for |
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LP2995 SNVS190M LP2995 WQFN-16 51C SOIC8 | |
51a soic8Contextual Info: LP2995 www.ti.com SNVS190M – FEBRUARY 2002 – REVISED MARCH 2013 LP2995 DDR Termination Regulator Check for Samples: LP2995 FEATURES DESCRIPTION • • • • • • • The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for |
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LP2995 SNVS190M LP2995 51a soic8 | |
2995M
Abstract: "2995m DDA0008A LP2995M 51C SOIC8
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LP2995 SNVS190L LP2995 WQFN-16 2995M "2995m DDA0008A LP2995M 51C SOIC8 | |
LP2995M
Abstract: 2995M 51C SOIC8
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LP2995 SNVS190L LP2995 WQFN-16 LP2995M 2995M 51C SOIC8 | |
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Contextual Info: LP2995 www.ti.com SNVS190M – FEBRUARY 2002 – REVISED MARCH 2013 LP2995 DDR Termination Regulator Check for Samples: LP2995 FEATURES DESCRIPTION • • • • • • • The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for |
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LP2995 SNVS190M LP2995 | |
TPA6132A2
Abstract: tpa6132 TLV320AIC3104 TLV320AIC33 TPA6132A2RTER TPA6132A2RTET 16w45
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TPA6132A2 SLOS597 25-mW TPA6132A2 tpa6132 TLV320AIC3104 TLV320AIC33 TPA6132A2RTER TPA6132A2RTET 16w45 | |
DS125RT410Contextual Info: DS110DX410 PRODUCT BRIEF Low Power Multi-Rate Quad Channel Retimer General Description Features The DS110DX410 is a four-channel multi-rate retimer with integrated signal conditioning. The DS110DX410 includes an input Continuous-Time Linear Equalizer CTLE on each |
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DS110DX410 DS125RT410 | |
DS125RT410Contextual Info: DS110DX410 PRODUCT BRIEF Low Power Multi-Rate Quad Channel Retimer Features General Description The DS110DX410 is a four-channel multi-rate retimer with integrated signal conditioning. The DS110DX410 includes an input Continuous-Time Linear Equalizer CTLE on each |
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DS110DX410 DS110DX410 DS125RT410 | |