JK FLIPFLOP 425 Search Results

74LS08 fan-in

Abstract: 74LS398 74LS273 74LS14 Hex Inverter definition MC74F579 74LS181 74ls795 74LS299 Decade Up/Down counter 3 State ttl buffer 74LS245
Contextual Info: Selection Information FAST/LS TTL 1 Circuit Characteristics 2 Design Considerations, Testing and Applications Assistance Form 3 FAST Data Sheets 4 LS Data Sheets 5 Reliability Data 6 Package Information Including Surface Mount 7 FAST AND LS TTL DATA CLASSIFICATION

Motorola u

Contextual Info: MOTOROLA U K . DUAL J-K MASTER-SLAVE FLIP-FLOP The MC10135 is a dual master-slave dc coupled J-K flip-flop. Asynchronous set S and reset (R )are provided. The set and reset inputs override the clock. _ A com mon clock is provided with separate J-K inputs. When

TA688

Abstract: 7input and gate ao1b AO11 TA164 TA-191 TA153 TA190 DLM8 TA273
Contextual Info: Integrator Series Macro Library – Tables of Hard, Soft, and TTL Macros Hard Macros—Combinatorial Modules Function Macro Description Combinatorial Logic Module CM8 Combinational Module Full 1200XL and 3200DX Logic Module Sequential Logic Module DFM7A

mc10135

Contextual Info: MOTOROLA DUAL J-K MASTER-SLAVE FLIP-FLOP The MC10135 is a dual master-slave dc coupled J-K flip-flop. Asynchronous set S and reset (R) are provided. The set and reset _ inputs override the clock. A com mon clock is provided w ith separate J-K inputs. When

592p

Abstract: 7292p 16 line to 4 line coder multiplexer 43s3a
Contextual Info: 1. HIGH SPEED CM O S PRODUCT GUIDE Type Number TC74HC TC74HC TC74HC TC74HC TC74HC Function OOAP/AF/AFN TOOAP/AF 02AP/AF/AFN T02AP/AF 03AP/AF/AFN 04AP/AF/AFN T04AP/AF/AFN U04AP/AF/AFN 05AP/AF 07AP/AF Q U A D 2-INPUT N A N O GATE 08AP/AF/AFN T08AP/AF 09AP/AF

bipolar PROM

Abstract: plhs18p8 S4LS04 82HS641 PLHS18 54175 82s137a 82S191 68172 54F04
Contextual Info: Signetics I Alphanumeric I Index Military Products H LM119 LM124 LM139 Vol. 1 17 Dual Voltage Comparator Vol.2 22 26 26 Low Power Quad Op Amp LM139A Qual Voltage Comparator Qual Voltage Comparator PLC18V8Z Zero Standby Power Universal PAL -Type Device PLC415

FZK101

Abstract: FZK105 upd101 SNF10 SN76131 TAA700 FZH111 FZJ101 MFC8010 MFC8001
Contextual Info: HANDBOOK OF INTESBATEI CIRCUITS in EQUIVALENTS AND SUBSTITUTES A lthough every care is taken with the preparation of this book, the publishers will not be responsible for any errors that might occur. I.S.B.N. 0 900162 35 X 1974 by Bernard B. Babani First Published 1974

BCD 4543

Abstract: 4564 RAM 4 bit binary pipeline ripple carry adder 4558, 4560 74F701
Contextual Info: S* Section 4 Contents 54F/74F00 Quad 2-Input NAND G a te . 54F/74F02 Quad 2-Input NOR G a te .

Contextual Info: m y D INTEGRATED CIRCUITS FROM MOTOROLA IS S U E A FUNCTIONS AND CHARACTERISTICS V CC = 5 .0 V , T a = 2 5 °C Type Function Case 609, 605, 632 0 to +75°C Case 6 09,632 -55 to +125°C Output Loading Factor Each Output MC500 MC400 Series Series Propagation

74AC367

Abstract: 74ACT705 74ac2526 74ac2525 54AC/74AC2525
Contextual Info: Section 4 Contents 54AC/74AC00 Quad 2-Input NAND G a te . 54ACT/74ACT00 Quad 2-Input NAND Gate .

hef4071bp

Abstract: HEC4051B HEF4752 octal Bilateral Switches 12 bit universal shift register HEF4534BP HEF4059BP 7-stage frequency divider HEF40374BD HEF4017BT
Contextual Info: J^ NUMERICAL INDEX extended type no. description page HEC4001BDB HEC40 feBDB HEC4007UBDB HEC40097BDB HEC40098BDB Quadruple 2-input NOR gate Dual 4-input NOR gate Dual complementary pair and inverter 3-state hex non-inverting buffer 3-state hex inverting buffer

Contextual Info: ATS42VA12 Features • • High-speed EPROM-based CMOS Multi-Function PLD Two Fully Programmable Arrays Eliminate "P-term Depletion" Up to 64 P-terms per OR Function Improved Output Macro Cell Structure Individually Programmable as: Registered Output with Feedback

TSMC 0.18 um MOSfet

Abstract: M38510 10102BCA IDT7204L 5962-8768401MQA 0.18um LDMOS TSMC sl1053 TSMC 0.25Um LDMOS UT63M125BB SMD RTAX250S-CQ208 5962-04221
Contextual Info: DSCC Supplemental Information Sheet for Electronic QML-38535 Specification Details: Date: 9/2/2008 Specification: MIL-PRF-38535 Title: Advanced Microcircuits Federal Supply Class FSC : 5962 Conventional: No Specification contains quality assurance program: Yes

ECL 10135

Abstract: 10135 jk flipflop 425 10135F 10135N 10135dc ecl 10K signetics
Contextual Info: Signetics 10135 Flip-Flop Dual J-K Master-Slave Flip-Flop P roduct Specification ECL Products DESCRIPTION The 10135 is a Dual Master-Slave DC coupled J-K Flip-Flop. It contains a com­ mon clock and separate J-K inputs which do not affect the output when the

Contextual Info: Philips Components 10135 Document No. 8 5 3 -0 6 6 4 EC N No. 99799 Date of Issue June 14, 1990 Flip-Flop Status Product Specification Dual J-K Master-Slave Flip-Flop ECL Products FEATURES • Typical propagation delay: 3.0ns • Typical supply current -lEE : 54mA

Contextual Info: Philips Components-Signetics 10135 Docum ent No. 8 5 3 -0 6 6 4 E C N No. 99799 D ate of Issue June 14, 1990 Status Product Specification Flip-Flop Dual J-K Master-Slave Flip-Flop EC L Products FEATURES • Typical propagation delay: 3.0ns • Typical supply current -tEE : 54mA

Contextual Info: GEC PLESSEY S E M I C O N D U C T O R S DS2322-2.1 ULA DS SERIES HIGH PERFORMANCE ARRAYS FOR 100MHz DIGITAL ASIC SYSTEMS S u p e rs e d e s J u n e 1990 ed ition GEC Plessey Semiconductors DS Series of ULAs has been developed specifically to provide a low pow er ASIC solution for

9300FM

Contextual Info: 9300 ZW \ National Jim Semiconductor 9300/DM9300 4-Bit Parallel-Access Shift Register General Description The 9300 4-bit registers feature parallel inputs, parallel out­ puts, JK serial inputs, shift/load control input, and a direct overriding clear. The registers have two modes of operation:

9300DMQB

Abstract: 9300FMQB DM9300N J16A N16E W16A 9300f
Contextual Info: g g National Æm Semiconductor 9300/DM9300 4-Bit Parallel-Access Shift Register General Description The 9300 4-bit registers feature parallel inputs, parallel out­ puts, JK serial inputs, shift/load control input, and a direct overriding clear. The registers have two modes of operation:

MC10135

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual J-K Master-Slave Flip-Flop MCI 0135 The MC10135 is a dual m aster-slave dc coupled J -K flip-flop. Asynchro­ nous set S and reset (R) are provided. The set and reset inputs override the _ clock. A common clock is provided with separate J -K inputs. When the clock is

Contextual Info: ATL80 Features * 0.8 n drawn gate length combined with triple level metal provides outstanding speed/power performance * Design translation of existing ASIC, PLD and FPGA designs provide for easy alternate sourcing with equivalent performance * All ATL80 arrays can operate at 5.0 volts and 3.3 volts for lowpower applications

atmel 819

Abstract: atmel h 208 atl80 atmel 823
Contextual Info: ATL80 Features * 0.8 |i drawn gate length combined with triple level metal provides outstanding speed/power performance * Design translation of existing ASIC, PLD and FPGA designs provide for easy alternate sourcing with equivalent performance * All ATL80 arrays can operate at 5.0 volts and 3.3 volts for lowpower applications

dilmon 28

Abstract: OA34
Contextual Info: bBE J> m 3 7 bflSEE 0 0 x 7 7 3 b 'lO'i GEC PLESSEY Si PLSB GEC PLESSEY SEMICONDS S E M I C O N D U C T O R S DS2322-2.1 ULA DS SERIES HIGH PERFORMANCE ARRAYS FOR 100MHz DIGITAL ASIC SYSTEMS Supersedes June 1990 edition GEC Plessey Semiconductors DS Series of ULAs has been

vhdl code for 8-bit BCD adder

Abstract: vhdl code for vending machine drinks vending machine circuit vending machine hdl led digital clock vhdl code respack 8 vending machine hdl structural vhdl code for multiplexers SR flip flop using discrete gates verilog code mealy for vending machine
Contextual Info: VHDL Reference Guide Using Foundation Express with VHDL Design Descriptions Data Types Expressions Sequential Statements Concurrent Statements Register and Three-State Inference Writing Circuit Descriptions Foundation Express Directives Foundation Express