LATCHES Search Results

54HC573

Contextual Info: SN54HC573, SN74HC573 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS D26B4. DECEMBER 1982-REVISED SEPTEMBER 1987 • High-Current 3-State Output Drive Bus-Lines Directly or Up to 15 LSTTL Loads • Bus-Structured Pinout Package Options Include Plastic "Small

56DL

Abstract: SN74AS841
Contextual Info: TYPES SN54ALS841, SN54AS841, SN54ALS842, SN54AS842 SN74ALS841, SN74AS841, SN74ALS842, SN74AS842 10-BIT BUS INTERFACE D TYPE LATCHES WITH 3 STATE OUTPUTS D 2 8 2 5 , DECEMBER 1983 • 3-State Buffer-Type Outputs Drive Bus-Lines Directly • Bus-Structured Pinout

Contextual Info: SN54HC563, SN74HC563 OCTAL D TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS D 2 6 8 4 , DECEMBER 1 9 8 2 -R E V IS E D SEPTEMBER 1987 • High-Current 3-State Output Drive Bus-Lines Directly or Up to 15 LSTTL Loads S N 5 4 H C 5 6 3 . . . J P AC KAG E S N 7 4 H C 5 6 3 . . . D W OR N P AC KA G E

1d4 cb

Contextual Info: SN54ABT16373A, SN74ABT16373A 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS S CB S160 - DE CE M B E R 1992 Members of the Texas Instruments Widebus Family SN54ABT16373A . . . WD PACKAGE SN74ABT16373A . . . DGG OR DL PACKAGE TOP VIEW State-of-the-Art EPIC-llB™ BiCMOS Design

bd 9d

Abstract: SN74ALS29841
Contextual Info: SN74ALS29841 10-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS S D A S 1 4 9 A - JU N E 1 9 8 8 - REVISED JA N U A R Y 1995 3-State Buffer-Type Outputs Drive Bus Lines Directly DW OR NT PACKAGE TOP VIEW Bus-Structured Pinout m Provides Extra Bus-Driving Latches

AC5947N

Abstract: HDSP-6508 AC5947NF 75498 AC5947 DIGITAL IC 7493 ic 7493 supply voltage power supply current 12 pin 4 digit 7 segment display SN7694N
Contextual Info: ADVANCED C IR C U IT S PRELIM INARY AC5947N 18-SEGMENT D IS P L A Y DRIVER 12/11/79 N O R N F D U AL-IN-LINE PACKAGE TO P VIEW On chip latches for the A S C II input data ’C Output enable for display blanking and duty cycle dimming u *[ »C •c ’[

Contextual Info: SN74LVC137 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER WITH ADDRESS LATCHES SCAS340 - MARCH 1994 » EPIC Enhanced-Performance Implanted CMOS Submicron Process • Typical V o lp (Output Ground Bounce) D, DB, OR PW PACKAGE (TOP VIEW) A[ B[ c[ Ü2A [ S2B[ G1[

SN741

Abstract: SN54176
Contextual Info: SN54176, SN54177, SN74176, SN74177 35-MHz PRESETTABLE DECADE AND BINARY COUNTERS/LATCHES M A Y 1 9 7 1 - R E V IS E D M A R C H 1988 Reduced-Power Versions of SN54196, SN 54197, SN74196, and SN74197 50-MHz Counters S N 5 4 1 7 6 , S N 5 4 1 7 7 . . . J PACKAGE

Contextual Info: SN74ALS373, SN74AS373, SN54ALS373, SN54AS373 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS 02661. APRIL 1982 - BEVISEO M A Y 1986 • • 8 Latches in a Sinaia Package • 3-S tate Bus-Driving True O utputs SN64ALS373, SN54AS373 j packag e SN74ALS373, SN74AS373 . . . DW Ofl N PACKAGE

Z62D

Contextual Info: TYPES SN54LS597, SN54LS598, SN74LS597, SN74LS598 8-BIT SHIFT REGISTERS WITH INPUT LATCHES 0 2 6 3 5 , J A N U A R Y 1 9 8 1 - R E V lS E D D E C E M B E R 1 9 8 3 S N 5 4 L S 5 9 7 . . . J PACKA GE S N 7 4 1 S 5 9 7 . . . J OR N PACKAGE 8 -B it Parallel Storage Register Inputs

Contextual Info: SN54HC533, SN74HC533 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS D 2 6 8 4 . DECEMBER 1 9 8 2 -R E V IS E D SEPTEMBER 1 9 8 7 • 8 Latches in a Single Package • High-Current 3-State Inverting Outputs Can Drive Up to 15 LSTTL Loads S N 5 4 H C S 3 3 . . . J PACKAGE

Contextual Info: SN74ALS137, SN74AS137, SN54ALS137 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES D2661, APRIL 1982 - REVISED M AY 1986 Combings Decoder and 3-Bit Addreis Latch SN54ALS137 . . . J PACKAGE SN74ALS137, SN74AS137 . . . D O R N PACKAGE Incorporates 2 Output Enables to Simplify

CIRCUIT DIAGRAM OF Bf 199

Contextual Info: TC4042BP/BF/BFN C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC4042B QUAD CLOCKED "D " LATCH_ TC4042B contains fo u r circuits o f "D " type latches having common CLOCK input and POLARITY input. W hen POLARITY input is placed at "H " level, D input appears

LS 7475

Abstract: C4408
Contextual Info: SN5475, SN5477, SN54LS75, SN54LS77. SN7475, SN74LS75 4 BIT BISTABLE LATCHES MAR CH 1 9 7 4 - each latch (TOP VIEW) OUTPUTS INPUTS REVISED M A R C H 1 9 8 8 SN 5475 , SN 54LS75 . . . J OR W PACKAGE S N 7475 . . . N PACKAGE SN 74LS 75 . . . D O R N PACKAGE

Contextual Info: SN74ALVC16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS JANUARY 1993 DGG OR DL PACKAGE TOP VIEW UBT (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Mode

Ct533

Contextual Info: SN54HCTS33, SN74HCT533 OCTAL 0 TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS 0 2 8 0 4 , M AR C H 1 9 8 4 -R E V IS E D SEPTEMBER 1987 S N 5 4 H C T 5 3 3 . . . J P AC KAG E SN74H C T533 D W OR N P AC KA G E Inputs are TTL-Voltage Compatible 8 Latches in a Single Package

SN74ALVC16601

Contextual Info: SN74ALVC16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCAS264 - JANUARY 1993 - REVISED MARCH 1994 | • Member of the Texas Instruments Wldebus Family • UBT™ Universal Bus Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent,

74AC11873

Contextual Info: 54AC11873, 74AC11873 DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS • 54A C 11 8 73 . . . J T P A C K A G E 3-State Buffer-Type Outputs Drive Bus 74AC 11B73 . . . D W OR N T P A C K A G E Lines Directly TOP V IE W • Bus-Structured Pinout • Flow -Through A rchitecture O ptim izes PCB

SN54ALS137

Contextual Info: SN74ALS137, SN74AS137, SN54ALS137 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES D2661, APRIL 1982 - REVISED MAY 1986 Combines Decoder and 3-Bit Address Latch Incorporates 2 Output Enables to Simplify Cascading SN54ALS137 . . . J PACKAGE SN74ALS137, SN74AS137 . . . D OR N PACKAGE

74AC11533

Abstract: 123D20
Contextual Info: *»4AP11*511 744011*511 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS TI0085— D2957, JULY 1987— REVISED JAN U AR Y 1990 54AC11533 . . . JT PACKAGE 74AC11533 . . . DW OR NT PACKAGE • 8-Latches in a Single Package • 3-State Bus-Driving Inverting Outputs

SN74ALS563A

Contextual Info: SN54ALS563A, SN74ALS563A OCTAL D TYPE TRANSPARENT LATCHES WITH 3 STATE OUTPUTS D 2 6 6 1 , DECEMBER 1 9 8 2 -• REVISED M A Y 1 9 8 6 3-State Buffer-Type Outputs Drive Bus-Lines Directly SN 54A LS5 63A . . J PACKAG E S N 7 4 A L S 5 6 3 A . . . DW OR N P A C KA G E

als844

Abstract: b83q SN74AS843
Contextual Info: TYPES SN54ALS843, SN54AS843, SN54ALS844, SN54AS844 SN74ALS843, SN74AS843, SN74ALS844, SN74AS844 9 BIT BUS INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS DECEMBER 1 9 8 3 3-S tate Buffer-Type Outputs Drive Bus-Lines Directly S N 5 4 A L S 8 4 3 . S N S 4 A S 8 4 3 . . . J T PACKAGE

TC4042BP

Abstract: IS902
Contextual Info: TC4042BP/BF C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC4042BP/TC4042BF QUAD CLOCKED "D" LATCH TC4042BP/BF contains four circuits of MD" type latches having common CLOCK input and POLARITY input. When POLARITY input is placed at "H" level, D input

74ls597

Abstract: 74LS59B
Contextual Info: SN54LS597, SN 54LS598, SN74LS597. SN 74LS59B 8 BIT SHIFT REGISTERS WITH INPUT LATCHES 02635 8-Bit Parallel Storage Register Inputs 'LS597J JA N U A R Y 1981 - REVISED M AR C H 1988 S N 5 4 L S 5 9 7 . . . J OR W P AC KA G E S N 7 4 L S 5 9 7 . . . N P AC KA G E