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    LATCHES 74373 Search Results

    LATCHES 74373 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TCKE800NL Toshiba Electronic Devices & Storage Corporation eFuse IC (electronic Fuse), 4.4 to 18 V, 5.0 A, Latch, WSON10B Visit Toshiba Electronic Devices & Storage Corporation
    TCKE812NL Toshiba Electronic Devices & Storage Corporation eFuse IC (electronic Fuse), 4.4 to 18 V, 5.0 A, Latch, Fixed Over Voltage Clamp, WSON10B Visit Toshiba Electronic Devices & Storage Corporation
    TCKE712BNL Toshiba Electronic Devices & Storage Corporation eFuse IC (electronic Fuse), 4.4 to 13.2 V, 3.65 A, Latch, Adjustable Over Voltage Protection, WSON10 Visit Toshiba Electronic Devices & Storage Corporation
    TCTH022AE Toshiba Electronic Devices & Storage Corporation Over Temperature Detection IC / VDD=1.7~5.5V / IPTCO=10μA / IDD=11.3μA / Push-pull type / FLAG signal latch function Visit Toshiba Electronic Devices & Storage Corporation
    TCTH022BE Toshiba Electronic Devices & Storage Corporation Over Temperature Detection IC / VDD=1.7~5.5V / IPTCO=10μA / IDD=11.3μA / Open-drain type / FLAG signal latch function Visit Toshiba Electronic Devices & Storage Corporation

    LATCHES 74373 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    74171

    Abstract: 7478 J-K Flip-Flop 7478 jk 74594 7400 series logic ICs shift register by using D flip-flop 7474 7498 4 bit 74395 74822 74278
    Text: QAN1 Registers and Latches in the pASIC Architecture INTRODUCTION Quicklogic’s pASICTM 1 Family of high-performance FPGAs allows logic function speeds of over 100 MHz. The prime objective of the QuickLogic pASIC 1 Family logic cell is to maximize in-system device speed, while


    Original     		PDF QL8X12B, 16-bit QL8X12 1000-gate 74171 7478 J-K Flip-Flop 7478 jk 74594 7400 series logic ICs shift register by using D flip-flop 7474 7498 4 bit 74395 74822 74278

    full subtractor circuit using xor and nand gates

    Abstract: 74138 full subtractor 3-input-XOR 74138 decoder 7474 D flip-flop vhdl code for 8-bit BCD adder data sheet 74139 vhdl code for 8 bit ODD parity generator 74171 74594
    Text: Chapter 10 - Macro Library Reference Chapter 10: The Macro Library The QuickLogic Macro Library contains over 475 macros and macro building blocks. While these macros offer a wide range of functions and flexibility, they fall into familiar functional groups. The naming conventions employed in the library are easy


    Original     		PDF

    7474 D flip-flop

    Abstract: vhdl code for 74154 4-to-16 decoder 7478 J-K Flip-Flop vhdl code for 74194 74138 full subtractor 3-8 decoder 74138 shift register by using D flip-flop 7474 full subtractor circuit using xor and nand gates vhdl code for 8-bit BCD adder 74823 FULL ADDER
    Text: Chapter 3 - Macro Library Reference Chapter 3: The Macro Library The QuickLogic Macro Library contains over 500 macros and macro building blocks. While these macros offer a wide range of functions and flexibility, they fall into familiar functional groups. The naming conventions employed in the library are easy


    Original     		PDF

    74573

    Abstract: 74574 7486 XOR GATE 7486 full adder latch 74574 7408, 7404, 7486, 7432 7490 Decade Counter 74373 cmos dual s-r latch 2 bit magnitude comparator using 2 xor gates design a BCD counter using j-k flipflop
    Text: Semiconductor Logic Device Cross-Reference Here is a comprehensive cross-reference of TTL and CMOS chips that are readily available over the counter from such places as Maplin Electronics in the UK . Tables of both TTL and CMOS devices are provided along with tables grouping chips with the same functionality together.


    Original     		PDF

    QL24X32B-1PF144C

    Abstract: vhdl code for 74194 QP-PL84G 74164 pin assignment ls 74138 74139 for bcd to excess 3 code PQ208 QL8X12B PF144 16 bit ripple adder
    Text: QuickTools User's Guide with SpDE™ Reference January 1996 Copyright Information Copyright 1991, 1992, 1993, 1994, 1995 QuickLogic Corporation. All rights reserved. The information contained in this manual and the accompanying software program are protected by copyright; all rights are reserved by QuickLogic Corporation. QuickLogic


    Original     		PDF Win32s, QL24X32B-1PF144C vhdl code for 74194 QP-PL84G 74164 pin assignment ls 74138 74139 for bcd to excess 3 code PQ208 QL8X12B PF144 16 bit ripple adder

    LM 74138

    Abstract: 74373 latch ic ic 74373 D latch function of latch ic 74373 truth table for ic 74138 specifications of 74373 latch ic pin DIAGRAM OF IC 74240 Latches 74373 IC 74373 truth table IC 74373 pin diagram
    Text: intei 82303 LOCAL I/O SUPPORT CHIP • High Integration—The 82304, 82303and 82077 Floppy Disk Controller Replace 50 IC’s in IBM Design ■ Supports System Board Setup B |ntegrated peripheral Bus Address Latches ■ ■ Integrated Parallel Port Integrated Card Setup Port 96H


    OCR Scan     		PDF 82303and P103WR# 103WR# 103RD# P103RD# P101RD# LM 74138 74373 latch ic ic 74373 D latch function of latch ic 74373 truth table for ic 74138 specifications of 74373 latch ic pin DIAGRAM OF IC 74240 Latches 74373 IC 74373 truth table IC 74373 pin diagram

    82303

    Abstract: No abstract text available
    Text: in te i 82303 LOCAL I/O SUPPORT CHIP • High Integration—The 82304, 82303 and Fl°ppy DiskContro|er Replace 50 IC’s in IBM Design ■ Supports System Board Setup B ,ntegrated Peripheral Bus Address Latches ■ Integrated Parallel Port a Low pQWer CHMOS Technology


    OCR Scan     		PDF M60STR# 82303

    74373

    Abstract: 74363 74573 74563 74580 1/LM 74373
    Text: —208 — 74363 Octal 3-5>tate D -Latches •o ao 70 70 B U tO 0 - rfci1 & r ^ t /\ff% i I, i IjO [& 1M T , i r , L1 O 7 4 3 7 3 <7 ,4i J s n £ A - < U jM r1 , , C L . , 1) t 'IM O S > 9 ~ i * ffl) ] b it ~7 -y -f- 74363 IE e>« »a 74373 IE pm 74533 74563


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    74533

    Abstract: 74373 74573 74363
    Text: - 214- 74373 Octal 3-S!tate D-Latches r f c ? 8- $ f , A f ‘h r1 e i ^ 7 w fi't] t r J j _ d OUTPUT K O 8 b it 7 -y -f . o 7 -y +<r>W)m~'O^Xli.7475Z? t m ~ . o th tifrZ x r - h iz&~3 x ^ i, n 'C '< x O O u tp u t C o n tro l 'f -i > h ‘ - r > 0G = H


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    74573

    Abstract: 74373 latch 74373 74573 Latch TTL 74373 74363 Q506 74563
    Text: — 260 — Octal 3-State D-Latches 74573 _c QO Ql 02 03 Q4 Q5 06 07 G DO D1 D2 D3 D4 D5 D6 D7 GND i o 74373« O 74563IÌ la] t f > * « K t £ Q 9 -f o ie f f l S I i è 'i x t t i î l t ~f « S A Output C o n tr ol L L H f] m L a tc h E n a b le L H


    OCR Scan     		PDF 74563li 74573 74373 latch 74373 74573 Latch TTL 74373 74363 Q506 74563

    74573

    Abstract: 74841 74373 latch 74373 D2 6J
    Text: 313 — 74841 — 10-B it 3-State D-Latches V„ QO Ql Q? Q3 Qd Q5 o7 4 5 73 W 10 Bi t S Q7 Q9 G ms o 7 4 8 4 2 l± M tf> ffiio a fe A QE tl Q) 9 m if- O u tp u t C o n tr o l L a tc h E n a b le L L L H Q= D H X High-Z x ii IN till OUT N LS ALS ALSK F S


    OCR Scan     		PDF 10-Bit o74573W10BitiS o74842l 74573 74841 74373 latch 74373 D2 6J

    74573

    Abstract: 74373 Latches 74373
    Text: — 74843 9-Bit 3-State D-Latches with Common Preset and Common Clear 0 74573*7 9 B i t 7 * 'J - t - y o 7 4 8 4 4 [i|5 jt;t:> ^ l£ i& m i t 't i b m h, t) (Q ) ;M 7 ° t J] m C LR O E G H H L L H H L H X X H X L X L X H L L X Q II a PR H ig h - Z y j - t '/


    OCR Scan     		PDF o74844l 74573 74373 Latches 74373

    IC 74373

    Abstract: IC 74373 truth table logitech 99 mouse IC function of latch ic 74373
    Text: USER-CONFIGURABLE r Q Q 1 /1 0 0 MICROPROCESSOR PERIPHERAL E r D I ^ H J U \ GENERAL DESCRIPTION FEATURES Bus I/O — Register Intensive B U S T ER EPLD. Erasable, User-Configurable Logic Device for Customized Microprocessor Peripheral Functions. Byte-Wide Microprocessor Bus Port with


    OCR Scan     		PDF 32-bit 25MHz Dri22 EPB1400 IC 74373 IC 74373 truth table logitech 99 mouse IC function of latch ic 74373

    74245 BUFFER IC

    Abstract: pin diagram of 74245 BUFFER IC IC 74245 latch 74373 80386 microprocessor pin out diagram 74245 buffer 74373 cmos dual s-r latch 74245 BIDIRECTIONAL BUFFER data 74245 20 pin ic Ob2 tube
    Text: V 7 \ USER-CONFIGURABLE m ic r o p r o c e s s o r p e r ip h e r a l C D D 1/100 L rD I4 U U FEATURES GENERAL DESCRIPTION • Bus I/O — Register Intensive BUSTER EPLD. • Erasable, User-Configurable Logic Device for Customized Microprocessor Peripheral


    OCR Scan     		PDF 32-bit 25MHz EPB1400-2 EPB1400 100pF. 74245 BUFFER IC pin diagram of 74245 BUFFER IC IC 74245 latch 74373 80386 microprocessor pin out diagram 74245 buffer 74373 cmos dual s-r latch 74245 BIDIRECTIONAL BUFFER data 74245 20 pin ic Ob2 tube

    eb 102H

    Abstract: No abstract text available
    Text: intJ. 82304 LOCAL I/O SUPPORT CHIP High-lntegration— The 82304, 82303 and 82077 Floppy Disk Controller Replace 50 IC’s in IBM Design Supports VG A Controller on the Local Channel Integrates the OS/2 Optimized HOT A20 and HOT R ESET Functions Supports I/O Peripherals . . . Keyboard/


    OCR Scan     		PDF 132Pin 823Q4 eb 102H

    82306

    Abstract: 74590 pin configuration of ic 74373 8259 Programmable Peripheral Interface IC 8259 internal pin diagram pin diagram of ic 74373 74245 BIDIRECTIONAL BUFFER IC pin diagram of 74245 BUFFER IC function of latch ic 74373 8259 keyboard interface
    Text: intei 82304 LOCAL I/O SUPPORT CHIP High-lntegration—The 82304, 82303 and 82077 Floppy Disk Controller Replace 50 IC’s in IBM Design Integrates Programmable Timer Counters 0, 2 and 3 Supports VGA Controller on the Local Channel Supports I/O Peripherals . . . Keyboard/


    OCR Scan     		PDF Technology/132Pin RAMD11 RAMD12 82306 74590 pin configuration of ic 74373 8259 Programmable Peripheral Interface IC 8259 internal pin diagram pin diagram of ic 74373 74245 BIDIRECTIONAL BUFFER IC pin diagram of 74245 BUFFER IC function of latch ic 74373 8259 keyboard interface

    74194 shift register

    Abstract: 74377 register logicaps shift register by using D flip-flop 7474 74191 counter 74377 Latches 74373 altera logicaps TTL library 74374 74373 ttl 74191
    Text: €Pßl400 PROGRAMMABLE BUS PERIPHERAL FEATURES GENERAL DESCRIPTION • Bus I/O —Register Intensive Buster EPLD The EPB1400 (Buster) EPLD from Altera repre­ sents the firs t M icro proce ssor Peripheral UserConfigurable at the Silicon level. The device consists


    OCR Scan     		PDF 25MHz EPB1400 EPB1400 74194 shift register 74377 register logicaps shift register by using D flip-flop 7474 74191 counter 74377 Latches 74373 altera logicaps TTL library 74374 74373 ttl 74191

    latch 74373

    Abstract: 74373 truth table 74373 cmos dual s-r latch Latches 74373 74245 truth table TTL 74373 serial mouse logitech Altera EP1800 74377 74373 free
    Text: U S E R -C O N F IG U R A B L E M IC R O P R O C E S S O R P E R IP H E R A L EPB1400 GENERAL DESCRIPTION FEATURES Bus I/O — R egister Intensive BU STER EPLD. Erasable, U se r-C o n fig u ra b le L o g ic Device fo r C ustom ized M ic ro p ro ce sso r Peripheral


    OCR Scan     		PDF EPB1400 32-bit 25MHz latch 74373 74373 truth table 74373 cmos dual s-r latch Latches 74373 74245 truth table TTL 74373 serial mouse logitech Altera EP1800 74377 74373 free

    asynchronous 4bit up down counter using jk flip flop

    Abstract: counter 74168 Multiplexer 74152 3-8 decoder 74138 synchronous counter using 4 flip flip 74183 alu 7444 series Excess-3-gray code to Decimal decoder MH 74151 counter 74169 74169 SYNCHRONOUS 4-BIT BINARY COUNTER
    Text: • GENERAL DESCRIPTION T h e M S M 7 0 V 0 0 0 series is the gate array LSI based on the m aster slice m e th o d using the high p erfo rm an ce silicon gate 1.5 m ic ro n H C M O S process w ith th e d u a l-la y e r m etal structure. T his series has th e features to easily realize fu n c tio n s o f th e s c h m itt trigger, c ry s ta l/


    OCR Scan     		PDF MSM70V000 MSM70V000, asynchronous 4bit up down counter using jk flip flop counter 74168 Multiplexer 74152 3-8 decoder 74138 synchronous counter using 4 flip flip 74183 alu 7444 series Excess-3-gray code to Decimal decoder MH 74151 counter 74169 74169 SYNCHRONOUS 4-BIT BINARY COUNTER

    TTL 74139

    Abstract: 74153 mux MSI 74148 16cudslr CI 74138 sn 74373 8mcomp 7404 7408 7432 7408, 7404, 7486, 7432 Flip-Flop 7471
    Text: PLSLIB-TTL /$ ^ n^ X LIBRARY • TTL MacroFunction Library Diskette. • ADLIB, Altera Design Librarian Diskette. To increase design ease and productivity Altera has created M acroFunctions. These are high level building blocks that allow the user to design at


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    7408, 7404, 7486, 7432

    Abstract: RF400U functional diagram of 7400 and cd 4011 ls 7404 180 nm CMOS standard cell library TEXAS INSTRUMENTS 74191 4BITS s273 buffer 74374 7408 CMOS cmos 7404
    Text: TGC100 Series CMOS Gate Arrays RELEASE 3.0, REVISED JANUARY 1990 • Twelve Arrays with up to 26K Available Gates • Fast Prototype Turnaround Time • Extensive Design Support - Design Libraries Compatible with Daisy, Valid, and Mentor CAE Systems - Tl Regional ASIC Design Centers


    OCR Scan     		PDF TGC100 20-mA Sink/12mA TDB10LJ 120LJ TDC11LJ TDN11LJ 100MHz 7408, 7404, 7486, 7432 RF400U functional diagram of 7400 and cd 4011 ls 7404 180 nm CMOS standard cell library TEXAS INSTRUMENTS 74191 4BITS s273 buffer 74374 7408 CMOS cmos 7404

    7486 XOR gate

    Abstract: 8mcomp XOR 7486 Truth Table 74192 4count XOR 7486 GATE 16cudslr 7472 truth table 7486 xor 74194 truth table
    Text: PROGRAMMABL E a \ l o g ic s o f t w a r e I-WV i1 I— rT -U U PLS-MAX =Er - ]T — n V n i n ni l A V P L S -m A X MAX+PLUS FEATURES GENERAL DESCRIPTION • Unified Development system for the entire Multiple Array Matrix MAX family of EPLDs. • Multiple design entry methods including a hier­


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    AOI211

    Abstract: MX08 IC TTL 7400 schematic AOI33 8 bit full adder "8 bit full adder" LA01 BCD-TO-7-SEGMENT DECODER 74151H TR-C06
    Text: ÉNATL SEUICOND {MEMORY} OSE D | b S O llBb P 0 bl3Cm FGC Series t J^p^ Advanced 2-MlCrOll CMOS Gate Array Family fa T rc h T ld ASchlum bergerCom pany Description Array Organization The FGC Series is an advanced, high performance CMOS gate array family designed for LSI implementation of existing


    OCR Scan     		PDF FGC6000 7482H 7483H 7485H 7486H 7487H 74125H 74182H 74242H 74244H AOI211 MX08 IC TTL 7400 schematic AOI33 8 bit full adder "8 bit full adder" LA01 BCD-TO-7-SEGMENT DECODER 74151H TR-C06

    0221l

    Abstract: APPLICATION NOTES CD 7474 IC bit-slice TGC119 TGC100 IPF 830 RC02X ci 7432 ttl DTN20 tsg 271
    Text: TGC100 Series 1-|im CMOS Gate Arrays RELEASE 4.0. REVISED SEPTEMBER 1991 14 Arrays with up to 26K Available Gates C E LL C O LU M N Fast Prototype Turnaround Time W IR IN G C H A N N E L Extensive Design Support -Design Libraries Compatible With Valid,u and Mentor CAE Systems


    OCR Scan     		PDF TGC100 16-mA Slnk/12-mA 0221l APPLICATION NOTES CD 7474 IC bit-slice TGC119 IPF 830 RC02X ci 7432 ttl DTN20 tsg 271