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    pLSI 2032-80LJ

    Abstract: isplsi device layout
    Text: LATTS006 Lattice ispLS r and pLSI 2032 * High Density Programmable Logic Functional Block Diagram Features HIGH DENSITY PROGRAMMABLE LOGIC — — — — — 1000PLD Gates 32 I/O Pins, Two Dedicated Inputs 32 Registers High Speed Global Interconnect Wide Input Gating for Fast Counters, State


    OCR Scan     		PDF LATTS006 1000PLD 212-80Bisp/2000 2032-135LJ 2032-135LT 2032-110LJ 2032-110LT 2032-80LJ 2032-80LT pLSI 2032-80LJ isplsi device layout