LF3312 Search Results

Contextual Info: LF3312 12-Mbit Frame Buffer / FIFO DEVICES INCORPORATED Preliminary Datasheet Features 12,441,600-bit Frame Memory 74.25MHz Max Data Rate May be Organized Into the Following Configurations: • 1,555,200 x 8-bit single channel • 1,244,160 x 10-bit (single channel)

LF3312

Abstract: LF3312BGC position sensitive diode circuit
Contextual Info: LF3312 12-Mbit Frame Buffer / FIFO DEVICES INCORPORATED Preliminary Datasheet Features 12,441,600-bit Frame Memory 74.25MHz Max Data Rate May be Organized Into the Following Configurations: • 1,555,200 x 8-bit single channel • 1,244,160 x 10-bit (single channel)

LF3312

Contextual Info: Image Manipulation – Vertical Flip LF3312 - Application Note OVERVIEW With the LF3312’s flexible memory address architecture, data can be sequentially stored in memory and then accessed using a completely reordered address. An application such as creating the

LF3312

Contextual Info: LF3312 Product Brief DEVICES INCORPORATED 12Mbit Frame Buffer / FIFO Providing designers with a single-chip approach to Sequential and Random Data Access FEATURES: Configurable 12,441,600-bit Memory - Allocate as Single/Dual Channels - Selectable Input/Output Word Widths

LF3312

Abstract: DSA00113352
Contextual Info: Image Manipulation - Reflect Image on Vertical Axis DEVICES INCORPORATED Video Memory Application Note FRAME MEMORY Overview With the LF3312’s flexible memory address architecture, data can be sequentially stored in memory and then accessed using a completely reordered address. An application such as creating the ‘mirror image’ of a frame of

LF3312

Abstract: LF3312s LF33 12FC00
Contextual Info: Depth Expansion through Cascading LF3312 - Application Note OVERVIEW Cascading multiple LF3312s for depth expansion is easy. The usable 24bit address space is simply extended for every additional device that is cascaded. The LF3312 is cascaded in parallel, where the input of each device is tied together. The input data

LF3312 m

Abstract: LF3312 LF3312BGC
Contextual Info: LF3312 12-Mbit Frame Buffer / FIFO DEVICES INCORPORATED Preliminary Datasheet Features 12,441,600-bit Frame Memory 74.25MHz Max Data Rate May be Organized Into the Following Configurations: • 1,555,200 x 8-bit single channel • 1,244,160 x 10-bit (single channel)

LF3312

Abstract: reset
Contextual Info: Hard and Soft Resets - Using RESET Pin LF3312 - Application Note OVERVIEW The RESET pin can both reset the contents of the Configuration Registers back to their default states see datasheet and act as a ‘global W/R pointer reset’. There are two types of resets that can be accomplished using the RESET pin: Hard and Soft resets.

LF3312

Contextual Info: Picture-in-Picture or Multi-source Buffering LF3312 - Application Note OVERVIEW Multiple independent data/video streams can be written into a shared linear address space using multiple LF3312s. Picture in Picture applications can be implemented where multiple video feeds are

LF3312

Contextual Info: Image Manipulation – Mirror Image LF3312 - Application Note OVERVIEW With the LF3312’s flexible memory address architecture, data can be sequentially stored in memory and then accessed using a completely reordered address. An application such as creating the ‘mirror

Contextual Info: LF3312 12-Mbit Frame Buffer / FIFO DEVICES INCORPORATED Preliminary Datasheet Features 12,441,600-bit Frame Memory May be Organized Into the Following Configurations: • 1,555,200 x 8-bit single channel • 1,244,160 x 10-bit (single channel) • 1,036,800 x 12-bit (single channel)

Contextual Info: LF3312 12-Mbit Frame Buffer / FIFO DEVICES INCORPORATED Preliminary Datasheet Features 12,441,600-bit Frame Memory 74.25MHz Max Data Rate May be Organized Into the Following Configurations: • 1,555,200 x 8-bit single channel • 1,244,160 x 10-bit (single channel)

Contextual Info: LF3312 12-Mbit Frame Buffer / FIFO DEVICES INCORPORATED Advance Information Features 12,441,600-bit Frame Memory May be Organized Into the Following Configurations: • 1,555,200 x 8-bit single channel • 1,244,160 x 10-bit (single channel) • 1,036,800 x 12-bit (single channel)

Contextual Info: LF3312 12-Mbit Frame Buffer / FIFO DEVICES INCORPORATED Preliminary Datasheet Features 12,441,600-bit Frame Memory May be Organized Into the Following Configurations: • 1,555,200 x 8-bit single channel • 1,244,160 x 10-bit (single channel) • 1,036,800 x 12-bit (single channel)

Contextual Info: LF3312 12-Mbit Frame Buffer / FIFO DEVICES INCORPORATED Preliminary Datasheet Features 12,441,600-bit Frame Memory 74.25MHz Max Data Rate May be Organized Into the Following Configurations: • 1,555,200 x 8-bit single channel • 1,244,160 x 10-bit (single channel)

Contextual Info: LF3312 12-Mbit Frame Buffer / FIFO DEVICES INCORPORATED Advance Information FEATURES 12,441,600-bit Frame Memory May be Organized Into the Following Configurations: • 1,555,200 x 8-bit single channel • 1,244,160 x 10-bit (single channel) • 1,036,800 x 12-bit (single channel)

LF3312

Abstract: 19 214
Contextual Info: This application brief describes the LF3312’s programmable flag behaviour. The first section describes the Empty/Full threshold settings. The second section provides a simple example of how the flags react to enabled writes and reads to/from the memory.

LF3312

Contextual Info: Image Manipulation - Reflect Image on Horizontal Axis DEVICES INCORPORATED Video Memory Application Note FRAME MEMORY Overview With the LF3312’s flexible memory address architecture, data can be sequentially stored in memory and then accessed using a completely reordered address. An application such as creating the ‘vertical flip’, or upside-down

LF3312

Abstract: 27MHZ
Contextual Info: Frame Delay of Digital Component Video LF3312 - Application Note OVERVIEW It is sometimes necessary to buffer fields or frames in a completely synchronous, delay-line fashion. This is often the case when comparing the current frame f with previous frames (f-1), (f-2), and so

marking apf

Abstract: LF3312 LF3312BGC
Contextual Info: LF3312 12-Mbit Frame Buffer / FIFO DEVICES INCORPORATED Preliminary Datasheet Features 12,441,600-bit Frame Memory May be Organized Into the Following Configurations: • 1,555,200 x 8-bit single channel • 1,244,160 x 10-bit (single channel) • 1,036,800 x 12-bit (single channel)

LF3312

Contextual Info: LF3312 12-Mbit Frame Buffer / FIFO DEVICES INCORPORATED Advance Information Features 12,441,600-bit Frame Memory May be Organized Into the Following Configurations: • 1,555,200 x 8-bit single channel • 1,244,160 x 10-bit (single channel) • 1,036,800 x 12-bit (single channel)

LF3312

Abstract: BUFFER FIFO
Contextual Info: OVERVIEW The basis for a frame synch system is managing the distance between Write and Read pointers of a Frame Buffer FIFO such as the LF3312. Frame tearing can easily occur in un-managed frame synchronization systems. Frame tearing occurs as the pointers sweep across each other, sometimes

LF3312

Abstract: VIDEO FRAME LINE BUFFER block DIAGRAM OF random access memory sequential MEMORY line
Contextual Info: De-interlacing – Video Storage LF3312 - Application Note Let the LF3312 Frame Buffer be the storage workhorse for your de-interlacing application. There is an increasing need for high performance de-interlacing systems as we convert more and more media into progressive scan format for consumption. The LF3312 is well

LF3312

Abstract: video stream
Contextual Info: Video Synchronization LF3312 - Application Note OVERVIEW The LF3312 is good tool for synchronizing video or data streams with arbitrary timing to a set system or ‘master’ timing source. The timing sources are typically in the form of a Clock and a field/frame