LKT 108 Search Results

lkt 108

Contextual Info: DATA SHEET NEC/ MOS INTEGRATED CIRCUIT ADVANCED ATM SONET FRAMER The ^¡PD98404 NEASCOT-P30 is an LSI for ATM applications, which can be used in ATM adapter boards for connecting PCs or workstations to an ATM network and can also be used in ATM hubs and ATM switches. This LSI

Contextual Info: TNETC2080 UNCHANNELIZED MULTI-PROTOCOL COMMUNICATIONS CONTROLLER Compatible With Texas Instruments Tl ATU-C Solution for Asymmetrical Digital Subscriber Line (ADSL) • High-Level Data-Link Control (HDLC) Data Mode - Complies With ISO 3309 - Automatic Flag Detection/Generation

Contextual Info: C U B IT Device C eîîB us Switch TXC-05801 DATA SH EE T FEATURES DESCRIPTION • U TO PIA or A LI-25 physical-layer cell interface C U B IT is a single-chip solution fo r im plem enting low -cost ATM m ultiplexing and sw itching system s, based on the CellBus architecture. Such system s are

Contextual Info: DATA SHEET NEC MOS INTEGRATED CIRCUIT ¿ iP D 9 8 4 1 1 ATM QUAD SONET FRAMER T h e ^¡P D 98411 N E A S C O T -P 4 0 is one o f A T M -LA N LSIs and provides the fu n ctio n s o f the T C sub la yer o f the S O N E T /S D H -b a se physical layer o f the ATM protocol spe cifie d by the ATM Forum .

24c02 eeprom

Abstract: da qz transistor
Contextual Info: TNETX3270 ThunderSWITCH 24/3 ETHERNET™ SWITCH WITH 2410-MBIT/S PORTS AND 310-/100-MBIT/S PORTS S P W S 0 4 3 B - N O VE M B ER 1997 - R EVISED A P R IL 1999 Port Configurations: Twenty-Four 10-Mbit/s Ports - Ports Arranged in Three Groups ot Eight Ports in a Multiplexed Interface

150L

Abstract: 1N3092 1N3111 1N3288A 1N3296A B-42 weight D0-205AC
Contextual Info: Bulletin 12037 International ^Rectifier S E R I E S 45L R , 150K / L / K S ( R ) Stud Version STANDARD RECOVERY DIODES Features • Alloy diode ■ High current carrying capability ■ High voltage ratings up to 1000V ■ High surge current capabilities

Contextual Info: tmän S w it c h x- „ L3M Device Level 3 Mapper TXC-03452B DATA SHEET FEATURES DESCRIPTION ^ • Maps DS3 44.736 Mbit/s or E3 (34.368 Mbit/s) line formats into S D H /S O N E T formats as follows: - DS3 to/from STM-1/TUG-3 - DS3 to/from STS-3/STS-1 S P E or STS-1 S P E

Contextual Info: PRELIMINARY DATA SHEET NEC MOS INTEGRATED CIRCUIT 2.4G bps ATM SONET FRAMER The ,uPD98414 NEASCOT-P70 is one of ATM LSIs and provides the functions of the TC sublayer of the SONET/SDH-base physical layer of the ATM protocol specified by the ATM Forum.

LA 42032

Abstract: opti 82C802 HT-88 82C802 82C822 SiS chipset 486 486dlc 82c802g 82C601 amd-486
Contextual Info: • ftlIP H M [ iiL IU ll 82C802GP System/Power Management Controller 1.0 * Features - Supports CPUs with L1 write-back feature Processor interface: - Intel 80486SX, DX, DX2, SLe, DX4, P24T, P24D • - AMD® 486DX, DX2, DXL, DXL2, Plus - Cyrix® DX, DX2, M7

ABT16374A

Abstract: SN54ABT16374A SN74ABT16374A
Contextual Info: SN54ABT16374A, SN74ABT16374A 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS _ S C B S 2 0 5 A - M ARCH 1 9 9 3 -R E V IS E D JULY 1994 Members of the Texas Instruments Wldebus Family State-of-the-Art EPIC-IIB™ BICMOS Design

vhdl code for loop filter of digital PLL

Abstract: vhdl code for frequency divider
Contextual Info: LatticeECP2/M sysCLOCK PLL/DLL Design and Usage Guide October 2009 Technical Note TN1103 Introduction This user’s guide describes the clock resources available in the LatticeECP2 and LatticeECP2M™ device architectures. Details are provided for primary clocks, secondary clocks and edge clocks, as well as clock elements

MC5246

Abstract: MC-5246 J15H
Contextual Info: flXILINX 108-Macrocell CMOS CPLD January, 1997 Version 1.0 Product Specification Features M acrocells can individually be specified for high perfor­ mance or low power operation by adding attributes to the logic schematic, or declaration statem ents to the behavioral

Contextual Info: LatticeECP2/M sysCLOCK PLL/DLL Design and Usage Guide June 2010 Technical Note TN1103 Introduction This user’s guide describes the clock resources available in the LatticeECP2 and LatticeECP2M™ device architectures. Details are provided for primary clocks, secondary clocks and edge clocks, as well as clock elements

csr bc7

Abstract: YGV604 at3 block diagram
Contextual Info: Y A M A H A ' L S ¿ YGV604 V S G Video Screen Generator • Outline H igh level display functio n ality and a high speed d raw ing function m akes V SG the ideal V D P to control c o n su m er television display screens. A variety o f graphic system s can be easily constructed, for exam ple; video

82C801

Abstract: 486DLC/IBM opti 486 chipset
Contextual Info: E ili iìj é u n SAHJU 82C802GP System/Power Management Controller 1.0 • Features - Supports CPUs with L1 write-back feature Processor interface: - Intel 80486SX, DX, DX2, SLe, DX4, P24T, P24D • - AMD® 486DX, DX2, DXL, DXL2, Plus - Cyrix® DX, DX2, M7

Contextual Info: COBRA Device Constant Bit Rate ATM Adaptation Layer 1 TXC-05427 FEATURES i , —- = DATA SHEET Product Preview = DESCRIPTION COBRA C o nstant Bit Bate ATM Adaptation Layer 1 is a four-channel VLSI device that implements all of the functions needed for circuit emulation over ATM. Both

Contextual Info: TNETX3110 ThunderSWITCH 8/3 ETHERNET™ SWITCH WITH EIGHT 10-MBIT/S PORTS AND THREE 10-/100-MBIT/S PORTS SP W S04 7- MARCH 1998 Port Configurations: Eight 10-Mbit/s Ports - Ports Arranged in One Group of Eight Ports in a Multiplexed Interface - Direct Multiplexer Interface to

Contextual Info: PM P r e v ie w In fo r m a tio n Datasheet • ■ T# ■^ PMC-960758 ISSUE 3 PM C -Sierra, Inc. p m 7364Fr e e d m FRAME RELA Y PROTOCOL ENGINE AND DATA LINK MANAGER PM7364 FREEDM FRAME RELAY PROTOCOL ENGINE AND DATALINK MANAGER DATA SHEET Preview Information

Contextual Info: IBM11M32730B IBM11M32730C 32M x 72 DRAM MODULE Features • 32Mx72 Dual Bank Fast Page Mode DIMM System Performance Benefits: -Buffered inputs (except RAS, Data) -Reduced noise (32 Vss/Vcc Pir|s) -4 Byte Interleave enabled -Buffered PDs • Performance:

Contextual Info: DATA SHEET_ NEC MOS INTEGRATED CIRCUIT /¿ P D 9 8 4 0 1 A ATM SAR CHIP DESCRIPTION The ^¡PD98401A NEASCOT-S15 is a high-performance SAR chip that segments and reassembles ATM cells. This chip can interface with an ATM network when it is included in a workstation, computer, front-end processor,

Contextual Info: L3M Device Level 3 Mapper TXC-03452B DATASHEET FEATURES DESCRIPTION = The L3M maps a DS3 line signal into an STM-1 TUG-3 or STS-3/STS-1 SPE or STS-1 SPE SDH/SONET sig­ nal. An E3 line signal is mapped into an STM-1 TUG-3 signal only. The L3M provides a TUG-3 formatted signal

stb jtag

Contextual Info: PRELIMINARY DATA SHEET NEC MOS INTEGRATED CIRCUIT ATM SAR CHIP The ¿ì PD98401A NEASCOT-S15 is a high-performance SAR chip that segments and reassembles ATM cells. This chip can interface with an ATM network when it is included in a workstation, computer, front-end processor,

Contextual Info: SIEMENS ICs for Communications Analog Network Interface Circuit AN 1C PSB 4450 Version 1.1 PSB 4451 Version 1.1 Preliminary Data Sheet 02.99 DS 4 Revision History: Current Version: 02.99 Previous Version: none Page Page in previous (in current Version Version)

Contextual Info: „ tm ä n S w it c h QT1M Device Quad T1 Mapper TXC-04251 x- DATA SHEET FEATURES DESCRIPTION • Add/drop four 1.544 Mbit/s signals from an STS-1, an STS-3/AU-3, or an STM-1 VC-4 The Quad T1 Mapper device is designed for add/drop multiplexer, terminal multiplexer, and dual and single