LV161 Search Results

SN74LV161

Contextual Info: LV161A, LV161A 4ĆBIT SYNCHRONOUS BINARY COUNTERS SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 9.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D D D D D CLR CLK A B C D ENP GND 1 16 2 15 3 14 4

Contextual Info: ISSI IS 4 1 C 1 6 1 0 0 IS 4 1 L V 1 6 1 0 0 1M x 16 16-MBIT DYNAMIC RAM WITH EDO PAGE MODE PRELIMINARY AUGUST 1999 DESCRIPTION FEATURES The IS S I IS41C16100 and LV16100/are 1,048,576 x 16bit high-performance CMOS Dynamic Random Access Memo­ ries. These devices offer an accelerated cycle access called

Contextual Info: IS 4 1 C 1 6 1 0 0 /S IS 4 1 L V 1 6 1 0 0 /S 1M x 16 16-MBIT DYNAMIC RAM WITH EDO PAGE MODE ISSI PRELIMINARY OCTOBER 1998 DESCRIPTION FEATURES The ISSI IS41C16100/S and LV16100/S are 1,048,576 x 16-bit high-performance CMOS Dynamic Random Access Memories. These devices offer an accelerated cycle access

Contextual Info: LV161A, LV161A 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS404C – APRIL 1998 – REVISED JULY 2003 D D D D D D D D CLR CLK A B C D ENP GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC RCO QA QB QC QD ENT LOAD LV161A . . . FK PACKAGE TOP VIEW A B NC

AT49LV161-70TI

Abstract: 30H22 1427k
Contextual Info: Features • Single Voltage Read/Write Operation: 2.65V to 3.3V BV , 3.0V to 3.6V (LV) • Access Time – 70 ns • Sector Erase Architecture • • • • • • • • • • • – Thirty-one 32K Word (64K Bytes) Sectors with Individual Write Lockout

Contextual Info: LV161A, LV161A 4ĆBIT SYNCHRONOUS BINARY COUNTERS SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 9.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D D D D D CLR CLK A B C D ENP GND 1 16 2 15 3 14 4

Contextual Info: LV161A, LV161A 4ĆBIT SYNCHRONOUS BINARY COUNTERS SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 9.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D D D D D CLR CLK A B C D ENP GND 1 16 2 15 3 14 4

7054F

Abstract: BC564A HA13563 AC123A HITACHI microcontroller H8 534 manual IC 74LS47 AC538 BC245A 2SK3235 HA13557
Contextual Info: INDEX General General Information Semiconductor Packages Sales Locations Microcontroller Microcontroller General MultiChipModules Smart Card Micro. Overview Micro. Shortform Micro. Hardware Manual Micro. Program. Manual Micro. Application Notes LCD Controller / Driver

LV161284

Abstract: 1284-II
Contextual Info: LV161284 19-BIT BUS INTERFACE SCLS426C – OCTOBER 1998 – REVISED NOVEMBER 2002 D D D D D D DGG OR DL PACKAGE TOP VIEW 4.5-V to 5.5-V VCC Operation 1.4-kΩ Pullup Resistors Integrated on All Open-Drain Outputs Eliminate the Need for Discrete Resistors

AT49BV160T

Abstract: AT49BV161 AT49BV161T AT49LV160 AT49LV161 AT49LV161T AT49BV160
Contextual Info: Features • Single Voltage Read/Write Operation: 2.65V to 3.3V BV , 3.0V to 3.6V (LV) • Access Time – 70 ns • Sector Erase Architecture • • • • • • • • • • • – Thirty-one 32K Word (64K Bytes) Sectors with Individual Write Lockout

SN74 schmitt trigger

Abstract: SDYU001 SN54LV00A SN54LV02A SN54LV04A SN54LV05A SN54LV08A SN54LV14A SN54LV32A SN54LV74A
Contextual Info: LVC and LV LowĆVoltage CMOS Logic Data Book 1998 Logic Products General Information LVC Gates and MSI LVC Octals LVC Widebus LVC 3.3-V to 5-V Translators and Cable Drivers LV Gates and MSI LV Octals Application Reports Mechanical Data LVC and LV Low-Voltage CMOS Logic

Contextual Info: LV161A, LV161A 4ĆBIT SYNCHRONOUS BINARY COUNTERS SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 9.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D D D D D CLR CLK A B C D ENP GND 1 16 2 15 3 14 4

A115-A

Abstract: C101 SN74LV161284
Contextual Info: LV161284 19-BIT BUS INTERFACE SCLS426C – OCTOBER 1998 – REVISED NOVEMBER 2002 D D D D D D DGG OR DL PACKAGE TOP VIEW 4.5-V to 5.5-V VCC Operation 1.4-kΩ Pullup Resistors Integrated on All Open-Drain Outputs Eliminate the Need for Discrete Resistors

Contextual Info: ISSI IS 4 1 C 1 6 1 0 0 /S IS 4 1 L V 1 6 1 0 0 /S 1M x 16 16-MBIT DYNAMIC RAM WITH EDO PAGE MODE PRELIMINARY JANUARY 1999 DESCRIPTION FEATURES The ISSI IS41C16100/S and LV16100/S are 1,048,576 x 16-bit high-performance CMOS Dynamic Random Access Memories. These devices offer an accelerated cycle access

AT49LV160

Abstract: ATMEL AT49bv161 AT49LV161-70TI nc 555 AT49BV160 AT49BV160T AT49BV161 AT49BV161T AT49LV161 AT49LV161T
Contextual Info: Features • Single Voltage Read/Write Operation: 2.65V to 3.3V BV , 3.0V to 3.6V (LV) • Access Time – 70 ns • Sector Erase Architecture • • • • • • • • • • • – Thirty-one 32K Word (64K Bytes) Sectors with Individual Write Lockout

AT49BV1604A

Abstract: AT49BV1604AT AT49BV1614A AT49BV1614AT AT49LV1614A AT49LV1614AT
Contextual Info: Features • Single Voltage Read/Write Operation: 2.65V to 3.3V BV , 3.0V to 3.6V (LV) • Access Time – 70 ns • Sector Erase Architecture • • • • • • • • • • • • – Thirty-one 32K Word (64K Bytes) Sectors with Individual Write Lockout

Contextual Info: LV161284 19-BIT BUS INTERFACE SCLS426C – OCTOBER 1998 – REVISED NOVEMBER 2002 D D D D D D DGG OR DL PACKAGE TOP VIEW 4.5-V to 5.5-V VCC Operation 1.4-kΩ Pullup Resistors Integrated on All Open-Drain Outputs Eliminate the Need for Discrete Resistors

Contextual Info: LV161A, LV161A 4ĆBIT SYNCHRONOUS BINARY COUNTERS SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 9.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D D D D D CLR CLK A B C D ENP GND 1 16 2 15 3 14 4

Contextual Info: LV161A, LV161A 4ĆBIT SYNCHRONOUS BINARY COUNTERS SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 9.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D D D D D CLR CLK A B C D ENP GND 1 16 2 15 3 14 4

A115-A

Abstract: C101 SN74LV161284
Contextual Info: LV161284 19-BIT BUS INTERFACE SCLS426C – OCTOBER 1998 – REVISED NOVEMBER 2002 D D D D D D DGG OR DL PACKAGE TOP VIEW 4.5-V to 5.5-V VCC Operation 1.4-kΩ Pullup Resistors Integrated on All Open-Drain Outputs Eliminate the Need for Discrete Resistors

IS41C16100

Abstract: IS41LV16100 Datex
Contextual Info: IS 4 1 C 1 6 1 0 0 IS 4 1 L V 1 6 1 0 0 1M x 16 16-MBIT DYNAMIC RAM WITH EDO PAGE MODE ISSI PRELIMINARY AUGUST 1998 DESCRIPTION FEATURES The IS S I IS41C16100 and LV16100 are 1,048,576 x 16-bit high-performance CMOS Dynamic Random Access Memories. These devices offer an accelerated cycle access

AT49BV160

Abstract: AT49BV160T AT49BV161 AT49BV161T AT49LV160 AT49LV161 AT49LV161T AT49lV160T
Contextual Info: Features • Single Voltage Read/Write Operation: 2.65V to 3.3V BV , 3.0V to 3.6V (LV) • Access Time – 70 ns • Sector Erase Architecture • • • • • • • • • • • – Thirty-one 32K Word (64K Byte) Sectors with Individual Write Lockout

Contextual Info: LV161A, LV161A 4ĆBIT SYNCHRONOUS BINARY COUNTERS SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 9.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D D D D D CLR CLK A B C D ENP GND 1 16 2 15 3 14 4

K4S641632K-UC75

Abstract: h8sx K4S641632K R1LV1616RSD-7SR samsung BCK0
Contextual Info: APPLICATION NOTE H8SX Family Transfer between Synchronous DRAM and External SRAM with EXDMAC Cluster Transfer Introduction The EXDMAC function is used to transfer data from the synchronous DRAM area (hereafter referred to as SDRAM) to the SRAM area in cluster transfer mode.