LVCMOS Search Results

NB6N11SMNG

Contextual Info: NB6N11S 3.3 V 1:2 AnyLevelE Input to LVDS Fanout Buffer / Translator Description The NB6N11S is a differential 1:2 Clock or Data Receiver and will accept AnyLevel input signals: LVPECL, CML, LVCMOS, LVTTL, or LVDS. These signals will be translated to LVDS and two identical

Contextual Info: EURO QUARTZ Frequency range 50.01MHz to 200MHz 15pF load Frequency range 50.01MHz to 320MHz (10pF load) LVCMOS Output Supply Voltage 3.3 VDC Ultra low jitter less than 1ps GF42 CMOS VCXO 11.4 x 9.6 x 2.5mm 4 pad SMD OUTLINE & DIMENSIONS DESCRIPTION GF42 VCXOs, are packaged in an industry-standard, 4 pad, 11.4mm

Frequency multiplier 1mHz 10MHz

Contextual Info: EURO QUARTZ Frequency range 50.01MHz to 800MHz LVCMOS Output Supply Voltage 3.3 VDC High Q fundamental mode crystal Low jitter multiplier circuit GW64 CMOS VCXO 11.4 x 9.6 x 4.7mm 6 pad SMD OUTLINE & DIMENSIONS DESCRIPTION GW64 VCXOs, are packaged in an industry-standard, 6 pad, 11.4mm

Contextual Info: DS90CR287,DS90CR288A DS90CR287/DS90CR288A +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-85 MHz Literature Number: SNLS056F DS90CR287/DS90CR288A +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-85 MHz General Description Features The DS90CR287 transmitter converts 28 bits of LVCMOS/

Crystal 32 MHz 12 pF

Contextual Info: PL610-6x 1.8V to 3.3V XO IC’s for 312.5kHz to 60MHz, with Standby FEATURES DESCRIPTION • Single IC to cover up to 60MHz output frequency.  Direct oscillation operation  Input Frequency: Fundamental crystal: o 10MHz to 60MHz  Output Frequency: LVCMOS

marking xt 12

Abstract: MTC1
Contextual Info: 1.8V to 3.3V XO IC’s for 156.25kHz to 60MHz, with Standby FEATURES DESCRIPTION • Single IC to cover up to 60MHz output frequency.  Direct oscillation operation  Input Frequency: Fundamental crystal: o 5MHz to 60MHz  Output Frequency: LVCMOS o 156.25kHz to 60MHz 2.5V & 3.3V

SY100EPT22V

Abstract: SY89322V SY89322VMGTR SY89322VMITR footprint mlf amkor exposed pad M9999-060809
Contextual Info: 3.3V/5V DUAL LVTTL/LVCMOS-to-DIFFERENTIAL LVPECL TRANSLATOR Micrel, Inc. SY89322V Precision Edge SY89322V FEATURES • ■ ■ ■ ■ ■ ■ ■ 3.3V and 5V power supply option 300ps typical propagation delay Differential LVPECL outputs PNP LVTTL inputs for minimal loading

E55361

Abstract: HCPL-050L HCPL-053L HCPL-250L HCPL-253L
Contextual Info: AgilentHCPL-250L/050L/253L/053L LVTTL/LVCMOS Compatible 3.3 V Optocouplers 1 Mb/s Data Sheet Features • Low power consumption • High speed: 1 Mb/s • LVTTL/LVCMOS compatible Description These diode-transistor optocouplers use an insulating layer between a

Contextual Info: K4M64163PH - R B G/F Mobile-SDRAM 1M x 16Bit x 4 Banks Mobile SDRAM in 54CSP FEATURES GENERAL DESCRIPTION • 1.8V power supply. The K4M64163PH is 67,108,864 bits synchronous high data • LVCMOS compatible with multiplexed address. rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits,

Contextual Info: SK100ELT23W Dual Differential PECL to CMOS/TTL Translator PRELIMINARY HIGH-PERFORMANCE PRODUCTS Description Features The SK100ELT23W is a dual differential PECL to CMOS/TTL or LVCMOS/LVTTL Translator. Since PECL Positive ECL levels are used, only positive VCC and

27BSC

Abstract: AS1154 AS1156
Contextual Info: D a ta S he e t A S 11 5 6 / A S 11 5 4 S i n g l e / D u a l LV D S D r i v e r 1 General Description 2 Key Features The AS1156/AS1154 is a Single/Dual Flow-Through LVDS Low-Voltage Differential Signaling Line Driver which accepts and converts LVTTL/LVCMOS input levels into LVDS output signals. The device is perfect for

LQFP32

Abstract: LQFP-32 MC100 MC100EPT622 MC100EPT622FA MC100EPT622FAR2
Contextual Info: MC100EPT622 3.3V LVTTL/LVCMOS to LVPECL Translator The MC100EPT622 is a 10- Bit LVTTL/LVCMOS to LVPECL translator. Because LVPECL Positive ECL levels are used only +3.3 V and ground are required. The device has an OR- ed enable input which can accept either LVPECL (ENPECL) or TTL/LVCMOS inputs

Contextual Info: CDCE949 CDCEL949 www.ti.com SCAS844D – AUGUST 2007 – REVISED MARCH 2010 Programmable 4-PLL VCXO Clock Synthesizer with 1.8V, 2.5V and 3.3V LVCMOS Outputs Check for Samples: CDCE949, CDCEL949 FEATURES • 1 • Member of Programmable Clock Generator Family

Contextual Info: Standard Products UT16MX110/111/112 Analog Multiplexer Preliminary Data Sheet January 24, 2012 FEATURES INTRODUCTION       The UT16MX110/111/112 are low voltage analog multiplexers with a convenient LVCMOS 3.3V digital interface. The analog muxes have Break-Before-Make architecture with a low

Contextual Info: EURO QUARTZ GW576 CMOS VCXO 7 x 5 x 1.8mm 6 pad SMD Frequency range 50.01MHz to 800MHz LVCMOS Output Supply Voltage 3.3 VDC High Q fundamental mode crystal Low jitter multiplier circuit DESCRIPTION GW576 VCXOs, are packaged in an industry-standard, 6 pad, 7mm x

Contextual Info: HD74SSTL16857 14-bit SSTL_2 Registered Buffer HITACHI ADE-205-223B Z Preliminary 3rd. Edition February 1999 Description The HD74SSTL16857 is a 14-bit registered buffer designed for 2.3 V to 3.6 V Vcc operation and LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input.

MachXO sysIO Usage Guide

Abstract: LCMXO256C-4M100C LCMXO2280 lcmxo640c-3tn100i LCMXO640C-3FT256C LCMXO1200 LCMXO256 LCMXO2280E-4M132I LVCMOS15 LVCMOS25
Contextual Info: MachXO Family Data Sheet Version 02.3_4W February 2007 MachXO Family Data Sheet Introduction April 2006 Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL

Contextual Info: NB3F8L3005C 3.3V / 2.5V / 1.8V / 1.5V 1:5 LVCMOS Fanout Buffer Description The NB3F8L3005C is a 2:1:5 Clock / Data fanout buffer operating on a 3.3 V / 2.5 V Core VDD and two flexible 3.3 V / 2.5 V / 1.8 V / 1.5 V VDDOx supplies which must be equal or less than VDD.

Contextual Info: ICS8701I LOW SKEW, ÷1, ÷2 CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS8701I is a low skew, ÷1, ÷2 Clock Generator. The low impedance LVCMOS outputs are designed to drive 50Ω series or parallel terminated transmission lines. The effective fanout can be increased from 20 to 40 by utilizing

Contextual Info: 16-Bit Long-Reach Video Automotive Grade SERDES ISL76322 Features The ISL76322 is a serializer/deserializer of LVCMOS parallel video data. The video data presented to the serializer on the parallel LVCMOS bus is serialized into a high-speed differential signal. This differential signal is converted back to parallel video

Contextual Info: ICS8535-01 LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO3.3V LVPECL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS8535-01 is a low skew, high performance 1-to-4 LVCMOS/LVTTL-to-3.3V LVPECL fanout buffer. The ICS853501 has two single ended clock inputs. the single ended clock

LVDS register

Contextual Info: CDCE72010 SCAS858C – JUNE 2008 – REVISED JANUARY 2012 www.ti.com Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor Check for Samples: CDCE72010 FEATURES 1 • • • • • • • • • • • • • • High Performance LVPECL, LVDS, LVCMOS

DS90CF365MTD

Abstract: DS90CF365 DS90C385 DS90C365 DS90C365MTD DS90C385MTD MTD56 SLC64A
Contextual Info: DS90C385/DS90C365 +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display FPD Link-85 MHz, +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link-85 MHz General Description The DS90C385 transmitter converts 28 bits of LVCMOS/ LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link.

XEP20

Abstract: SY100EPT20V SY100EPT20VZC SY100EPT20VZCTR SY10EPT20V SY10EPT20VZC SY10EPT20VZCTR
Contextual Info: Micrel, Inc. ECL Pro SY10EPT20V ECL Pro™ SY100EPT20V 5V/3.3V LVTTL/LVCMOS-to-DIFFERENTIAL LVPECL TRANSLATOR SY10EPT20V SY100EPT20V FEATURES • ■ ■ ■ ■ ■ ■ ■ 3.3V and 5V power supply options 300ps typical propagation delay Differential LVPECL output