LVDS 30P Search Results

Contextual Info: MAX9376 LVDS/Anything-to-LVPECL/LVDS Dual Translator General Description The MAX9376 is a fully differential, high-speed, LVDS/ anything-to-LVPECL/LVDS dual translator designed for signal rates up to 2GHz. One channel is LVDS/ anything-to-LVPECL translator and the other channel

Contextual Info: 19-2809; Rev 1; 10/09 LVDS/Anything-to-LVPECL/LVDS Dual Translator The MAX9376 is a fully differential, high-speed, LVDS/anything-to-LVPECL/LVDS dual translator designed for signal rates up to 2GHz. One channel is LVDS/anything-to-LVPECL translator and the other

JESD51-7

Abstract: MAX9376 MAX9376EUB 630ps
Contextual Info: 19-2809; Rev 1; 10/09 LVDS/Anything-to-LVPECL/LVDS Dual Translator The MAX9376 is a fully differential, high-speed, LVDS/anything-to-LVPECL/LVDS dual translator designed for signal rates up to 2GHz. One channel is LVDS/anything-to-LVPECL translator and the other

Contextual Info: CY2DL1504 1:4 Differential LVDS Fanout Buffer with Selectable Clock Input 1:4 Differential LVDS Fanout Buffer with Selectable Clock Input Features Functional Description • Select one of two differential LVPECL, LVDS, HCSL, or CML input pairs to distribute to four LVDS output pairs

MAX9376

Abstract: MAX9376EUB
Contextual Info: 19-2809; Rev 0; 4/03 LVDS/Anything-to-LVPECL/LVDS Dual Translator Features ♦ Guaranteed 2GHz Switching Frequency ♦ Accepts LVDS/LVPECL/Anything Inputs ♦ 421ps typ Propagation Delays ♦ 30ps (max) Pulse Skew ♦ 2psRMS (max) Random Jitter ♦ Minimum 100mV Differential Input to Guarantee

2DL15

Abstract: JESD78B CY2DL1504ZXI 2DL-15
Contextual Info: CY2DL1504 1:4 Differential LVDS Fanout Buffer with Selectable Clock Input Features Functional Description • Select between low-voltage positive emitter-coupled logic LVPECL or low-voltage differential signal (LVDS) input pairs to distribute to four LVDS output pairs

cy2dl1504

Contextual Info: CY2DL1504 1:4 Differential LVDS Fanout Buffer with Selectable Clock Input Features Functional Description • Select between low-voltage positive emitter-coupled logic LVPECL or low-voltage differential signal (LVDS) input pairs to distribute to four LVDS output pairs

2DL15

Abstract: 2DL-15 2VBQ
Contextual Info: CY2DL1504 1:4 Differential LVDS Fanout Buffer with Selectable Clock Input Features Functional Description • Select one of two differential LVPECL, LVDS, or CML input pairs to distribute to four LVDS output pairs ■ 30-ps maximum output-to-output skew

Contextual Info: CY2DL1504 1:4 Differential LVDS Fanout Buffer with Selectable Clock Input Features Functional Description • Select one of two differential LVPECL, LVDS, HCSL, or CML input pairs to distribute to four LVDS output pairs ■ 30-ps maximum output-to-output skew

Contextual Info: PI6LC48L0201 2-Output LVDS Networking Clock Generator Features Description ÎÎTwo differential LVDS output pairs The PI6LC48L0201 is a 2-output LVDS synthesizer optimized to generate Ethernet reference clock frequencies and is a member of Pericom’s HiFlex family of high performance clock solutions.

MC100EP210S

Abstract: MC100EP210SFA MC100EP210SFAR2 100EP MC100 QA050 EP210S
Contextual Info: MC100EP210S 2.5VĄ1:5 Dual Differential LVDS Compatible Clock Driver The MC100EP210S is a low skew 1–to–5 dual differential driver, designed with LVDS clock distribution in mind. The LVDS or LVPECL input signals are differential and the signal is fanned out to

MAX9220EUM

Contextual Info: MAX9210/MAX9214/ MAX9220/MAX9222 General Description The MAX9210/MAX9214/MAX9220/MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/ LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a separate supply,

Contextual Info: EURO QUARTZ GDF576 LVDS VCXO 7 x 5 x 1.8mm SMD VCXO 38.0MHz to 640.0MHz Frequency range 38MHz to 640MHz LVDS Output Supply Voltage 3.3 VDC Phase jitter 0.4ps typical Pull range from ±30ppm to ±150ppm DESCRIPTION GDF576 VCXOs are LVDS output VCXOs packaged in 6 pad 7mm x

Contextual Info: Tel : Fax : email : 0044 0 118 979 1238 0044 (0) 118 979 1283 info@actcrystals.com ACT9212LJ 7x5mm LOW PHASE JITTER LVPECL / LVDS OSCILLATOR ACT9312LJ 5x3.2mm LOW PHASE JITTER LVPECL / LVDS OSCILLATOR The ACT9212LJ / 9213LJ LVPECL & LVDS Oscillators are a series of miniature low profile devices allowing for frequencies from 38 to

Contextual Info: 19-2864; Rev 5; 11/07 Programmable DC-Balance 21-Bit Deserializers The MAX9210/MAX9214/MAX9220/MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a separate supply, allowing

Contextual Info: EURO QUARTZ GDF62 LVDS VCXO 11.4 x 9.6 x 2.5mm SMD VCXO 38.0MHz to 640.0MHz Frequency range 38MHz to 640MHz LVDS Output Supply Voltage 3.3 VDC Phase jitter 0.4ps typical Pull range from ±30ppm to ±150ppm OUTLINE & DIMENSIONS DESCRIPTION GDF62 VCXOs are LVDS output VCXOs packaged in 6 pad 11.4 x 9.6

Contextual Info: EURO QUARTZ GDW62 LVDS VCXO 750.0kHz to 800.0MHz 11.4 x 9.6 x 2.5mm 6 pad SMD Frequency range 750kHz to 800MHz LVDS Output Supply Voltage 3.3 VDC Phase jitter 2.35ps typical Pull range from ±30ppm to ±150ppm DESCRIPTION OUTLINE & DIMENSIONS GDW576 LVDS output VCXOs are packaged in 6 pad 7 x 5mm SMD.

Contextual Info: EURO QUARTZ GDW576 LVDS VCXO 7 x 5 x 1.8mm SMD VCXO 750.0kHz to 800.0MHz Frequency range 750kHz to 800MHz LVDS Output Supply Voltage 3.3 VDC Phase jitter 2.35ps typical Pull range from ±30ppm to ±150ppm DESCRIPTION OUTLINE & DIMENSIONS GDW576 LVDS output VCXOs are packaged in 6 pad 7 x 5mm SMD.

MAX9210

Abstract: MAX9215 MAX9222 DS90CR216A DS90CR218A MAX9220EUM
Contextual Info: 19-2864; Rev 3; 4/04 Programmable DC-Balance 21-Bit Deserializers The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/ MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a separate supply, allowing 1.8V to 5V output logic levels.

Contextual Info: EURO QUARTZ GDA576 LVDS VCXO 7 x 5 x 1.8mm SMD VCXO Frequency range 60MHz to 240MHz LVDS Output Supply Voltage 3.3 VDC Phase jitter 0.2ps typical Pull range from ±30ppm to ±150ppm DESCRIPTION GDA576 VCXOs are packaged in a 6 pad 7mm x 5mm SMD package. Typical phase jitter for GDA series VCXOs is 0.2 ps. Output is LVDS.

MAX9220EUM

Contextual Info: 19-2864; Rev 4; 3/05 Programmable DC-Balance 21-Bit Deserializers The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/ MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a separate supply, allowing 1.8V to 5V output logic levels.

GDF576

Contextual Info: EURO QUARTZ GDF576 LVDS VCXO 7 x 5 x 1.8mm SMD VCXO Frequency range 38MHz to 640MHz LVDS Output Supply Voltage 3.3 VDC Phase jitter 0.4ps typical Pull range from ±30ppm to ±150ppm DESCRIPTION GDF576 VCXOs are packaged in a 6 pad 7mm x 5mm SMD package. Typical phase jitter for GDF series VCXOs is 0.4 ps. Output is LVDS.

Contextual Info: 19-2864; Rev 4; 3/05 Programmable DC-Balance 21-Bit Deserializers The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/ MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a separate supply, allowing 1.8V to 5V output logic levels.

DS90CR216A

Abstract: DS90CR218A MAX9210 MAX9215 MAX9222
Contextual Info: 19-2864; Rev 4; 3/05 Programmable DC-Balance 21-Bit Deserializers The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/ MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a separate supply, allowing 1.8V to 5V output logic levels.