LVDS 40 PIN Search Results

Contextual Info: LVDS Convert Modules AX95601 SBC Services and Solutions LVDS Converter From Factor: ECX stacking module Controller: Xilinx XC3S200AN Connector: 2 x 40-pins LVDS connectors Dimention: 65 x 43 mm Applied for CAPA800 and CAPA801 Systems on Modules Embedded SBCs

Contextual Info: CY2DL1510 1:10 Differential LVDS Fanout Buffer 1:10 Differential LVDS Fanout Buffer Features Functional Description • Low-voltage differential signal LVDS input with on-chip 100  input termination resistor ■ Ten differential LVDS outputs ■ 40 ps maximum output-to-output skew

SLLS526

Abstract: SN65LVDS1021DB SN65LVDS1212 SN65LVDS1212DB SN65LVDS1021
Contextual Info: SN65LVDS1021/SN65LVDS1212 10 MHz TO 40 MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS526 – FEBRUARY 2002 D D D 100–400 Mbps Serial LVDS Data Payload Bandwidth at 10 MHz to 40 MHz System Clock Pin-Compatible Superset of NSM DS92LV1021/DS92LV1212 Chipset Serializer/Deserializer Power

SLLS526A

Contextual Info: SN65LV1021/SN65LV1212 10 MHz TO 40 MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS526A – FEBRUARY 2002 – REVISED APRIL 2002 D D D D 100–400 Mbps Serial LVDS Data Payload Bandwidth at 10 MHz to 40 MHz System Clock Pin-Compatible Superset of NSM DS92LV1021/DS92LV1212

serializer guide

Abstract: SLLS526E 8208 ns
Contextual Info: SN65LV1021/SN65LV1212 10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS526E – FEBRUARY 2002 – REVISED SEPTEMBER 2002 D D D D 100-Mbps to 400-Mbps Serial LVDS Data Payload Bandwidth at 10-MHz to 40-MHz System Clock Pin-Compatible Superset of NSM

40mhz receiver circuit

Contextual Info: SN65LV1021/SN65LV1212 10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS526F – FEBRUARY 2002 – REVISED NOVEMBER 2002 D D D D 100-Mbps to 400-Mbps Serial LVDS Data Payload Bandwidth at 10-MHz to 40-MHz System Clock Pin-Compatible Superset of NSM DS92LV1021/DS92LV1212

Contextual Info: SN65LV1021/SN65LV1212 10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS526D – FEBRUARY 2002 – REVISED AUGUST 2002 D D D D 100-Mbps to 400-Mbps Serial LVDS Data Payload Bandwidth at 10-MHz to 40-MHz System Clock Pin-Compatible Superset of NSM DS92LV1021/DS92LV1212

SLLS526C

Contextual Info: SN65LV1021/SN65LV1212† 10 MHz TO 40 MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS526C – FEBRUARY 2002 – REVISED MAY 2002 D D D D 100–400 Mbps Serial LVDS Data Payload Bandwidth at 10 MHz to 40 MHz System Clock Pin-Compatible Superset of NSM DS92LV1021/DS92LV1212

lvds 40 pin pinout

Abstract: MO-150 SN65LV1021 SN65LV1021DB SN65LV1212 SN65LV1212DB SN65LVDS1021 SN65LVDS1212 SLLS526F
Contextual Info: SN65LV1021/SN65LV1212 10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS526F – FEBRUARY 2002 – REVISED NOVEMBER 2002 D D D D 100-Mbps to 400-Mbps Serial LVDS Data Payload Bandwidth at 10-MHz to 40-MHz System Clock Pin-Compatible Superset of NSM DS92LV1021/DS92LV1212

MO-150

Abstract: SN65LV1021 SN65LV1021DB SN65LV1212 SN65LV1212DB SN65LVDS1021 SN65LVDS1212
Contextual Info: SN65LV1021/SN65LV1212 10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS526F – FEBRUARY 2002 – REVISED NOVEMBER 2002 D D D D 100-Mbps to 400-Mbps Serial LVDS Data Payload Bandwidth at 10-MHz to 40-MHz System Clock Pin-Compatible Superset of NSM DS92LV1021/DS92LV1212

MO-150

Abstract: SN65LV1021 SN65LV1021DB SN65LV1212 SN65LV1212DB SN65LVDS1021 SN65LVDS1212 SLLS526B
Contextual Info: SN65LV1021/SN65LV1212† 10 MHz TO 40 MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS526B – FEBRUARY 2002 – REVISED APRIL 2002 D D D D 100–400 Mbps Serial LVDS Data Payload Bandwidth at 10 MHz to 40 MHz System Clock Pin-Compatible Superset of NSM DS92LV1021/DS92LV1212

Contextual Info: SN65LV1021/SN65LV1212 10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS526F – FEBRUARY 2002 – REVISED NOVEMBER 2002 D D D D 100-Mbps to 400-Mbps Serial LVDS Data Payload Bandwidth at 10-MHz to 40-MHz System Clock Pin-Compatible Superset of NSM DS92LV1021/DS92LV1212

10-bit-serdes

Abstract: MO-150 SN65LV1021 SN65LV1021DB SN65LV1212 SN65LV1212DB SN65LVDS1021 SN65LVDS1212
Contextual Info: SN65LV1021/SN65LV1212 10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS526F – FEBRUARY 2002 – REVISED NOVEMBER 2002 D D D D 100-Mbps to 400-Mbps Serial LVDS Data Payload Bandwidth at 10-MHz to 40-MHz System Clock Pin-Compatible Superset of NSM DS92LV1021/DS92LV1212

SLLS526D

Contextual Info: SN65LV1021/SN65LV1212 10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS526D – FEBRUARY 2002 – REVISED AUGUST 2002 D D D D 100-Mbps to 400-Mbps Serial LVDS Data Payload Bandwidth at 10-MHz to 40-MHz System Clock Pin-Compatible Superset of NSM DS92LV1021/DS92LV1212

Contextual Info: DS92LV1021A DS92LV1021A 16-40 MHz 10 Bit Bus LVDS Serializer Literature Number: SNLS151F DS92LV1021A 16-40 MHz 10 Bit Bus LVDS Serializer General Description The DS92LV1021A transforms a 10-bit wide parallel LVCMOS/LVTTL data bus into a single high speed Bus

SNLS151F

Abstract: SNLS151
Contextual Info: DS92LV1021A DS92LV1021A 16-40 MHz 10 Bit Bus LVDS Serializer Literature Number: SNLS151F DS92LV1021A 16-40 MHz 10 Bit Bus LVDS Serializer General Description The DS92LV1021A transforms a 10-bit wide parallel LVCMOS/LVTTL data bus into a single high speed Bus

DS92LV1210TMSA

Contextual Info: DS92LV1021,DS92LV1210 DS92LV1021 and DS92LV1210 16-40 MHz 10 Bit Bus LVDS Serializer and Deserializer Literature Number: SNLS024B DS92LV1021 and DS92LV1210 16-40 MHz 10 Bit Bus LVDS Serializer and Deserializer General Description The DS92LV1021 transforms a 10-bit wide parallel CMOS/

LM98640QML

Abstract: LM98640
Contextual Info: LM98640QML LM98640QML Dual Channel, 14-Bit, 40 MSPS Analog Front End with LVDS Output Literature Number: SNAS461B LM98640QML Dual Channel, 14-Bit, 40 MSPS Analog Front End with LVDS Output General Description Features The LM98640QML is a fully integrated, high performance 14Bit, 5 MSPS to 40 MSPS signal processing solution for image

Contextual Info: DS92LV1023 DS92LV1023 40-66 MHz 10 Bit Bus LVDS Serializer Literature Number: SNLS049C DS92LV1023 40-66 MHz 10 Bit Bus LVDS Serializer General Description Features The DS92LV1023 is a 400 to 660 Mb/s serializer for highspeed unidirectional serial data transmission over FR-4

470 KILO OHM RESISTOR

Abstract: 1 kilo ohm resistor specifications 2DL15 cy2dl1510 purpose of 2.2 kilo ohm resistor tsoe CY2DL1510AZ
Contextual Info: CY2DL1510 1:10 Differential LVDS Fanout Buffer Features Functional Description • Low-voltage differential signal LVDS input with on-chip 100-Ω input termination resistor ■ Ten differential LVDS outputs ■ 40-ps maximum output-to-output skew ■ 600-ps maximum propagation delay

Contextual Info: DS92LV1212A DS92LV1212A 16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery Literature Number: SNLS071D DS92LV1212A 16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery General Description Features The DS92LV1212A is an upgrade of the DS92LV1212. It

Contextual Info: DS92LV1212 DS92LV1212 16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery Literature Number: SNLS050 DS92LV1212 16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery General Description Features The DS92LV1212 is an upgrade of the DS92LV1210. It

Contextual Info: DS92LV1212 DS92LV1212 16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery Literature Number: SNLS050 DS92LV1212 16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery General Description Features The DS92LV1212 is an upgrade of the DS92LV1210. It

LM98640

Contextual Info: LM98640 www.ti.com SNAS596 – JUNE 2012 LM98640 Dual Channel, 14-Bit, 40 MSPS Analog Front End with LVDS Output Check for Samples: LM98640 FEATURES APPLICATIONS • • • • • • • • • 1 2 • • • • Seialized LVDS Outputs LVDS Input Clock