LY6264 Search Results

CS16LV40963

Abstract: BS62LV4006 sram cross reference CS18LV40963 LY6264 Hynix Cross Reference cs18lv10245 cs18lv02560 LY621024 K6X1008C2D
Contextual Info: www.ashlea.co.uk 01793 783784 Low power SRAM Cross Reference Density Configuration 64K 8Kx8 256K 32Kx8 Lyontek LY6264 LY62L64 LY62256 LY62L256 LY62256 2.7-5.5 1M 128Kx8 64Kx16 LY621024 LY62L1024 LY62L6416 Samsung K6X0808C1D K6X0808T1D K6X1008C2D K6X1008T2D

Contextual Info: LY6264 8K X 8 BIT LOW POWER CMOS SRAM Rev. 2.3 FEATURES GENERAL DESCRIPTION „ Fast access time : 35/55/70ns „ Low power consumption: Operating current : 20/15/10mA TYP. Standby current : 1µA (TYP.) LL-version „ Single 2.7~5.5V power supply „ All inputs and outputs TTL compatible

LY6264

Abstract: ly626
Contextual Info:  LY6264 8K X 8 BIT LOW POWER CMOS SRAM Rev. 2.7 REVISION HISTORY Revision Rev. 1.0 Rev. 2.0 Rev. 2.1 Rev. 2.2 Rev. 2.3 Rev. 2.4 Rev. 2.5 Rev. 2.6 Rev. 2.7 Description Initial Issue Revised Vcc Range 4.5~5.5V => 2.7~5.5V Revised ISB1 Adding PKG type : skinny P-DIP

LY62256

Abstract: LY6264 LY62W51216 ly62w6416m ly62l1024 LY62W LY62 32KX8 8X13 LY621024
Contextual Info: Density Configuration Chip select Power 64K 8KX8 Dual CE Control CE#,CE2 2.7V~5.5V 256K 32KX8 Single CE Control (CE#) 2.7V~5.5V 2.7V~3.6V 2.7V~5.5V 1M 128KX8 Dual CE Control (CE#, CE2) 4.5V~5.5V 2.7V~3.6V 2.7V~5.5V Item no. LY6264 LY62256 LY62L256 LY62W256

ly6264

Contextual Info: LY6264 8K X 8 BIT LOW POWER CMOS SRAM Rev. 2.5 REVISION HISTORY Revision Rev. 1.0 Rev. 2.0 Rev. 2.1 Rev. 2.2 Rev. 2.3 Rev. 2.4 Rev. 2.5 Description Initial Issue Revised Vcc Range 4.5~5.5V => 2.7~5.5V Revised ISB1 Adding PKG type : skinny P-DIP Revised VIH min =2.4V, VIL(max)=0.6V

Contextual Info: LY626416 64K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Description Initial Issue Revised typos in page 1,4,5 35ns to 45ns Lyontek Inc. reserves the rights to change the specifications and products without notice.

Contextual Info: LY6264 8K X 8 BIT LOW POWER CMOS SRAM Rev. 2.8 REVISION HISTORY Revision Rev. 1.0 Rev. 2.0 Rev. 2.1 Rev. 2.2 Rev. 2.3 Rev. 2.4 Rev. 2.5 Rev. 2.6 Rev. 2.7 Rev. 2.8 Description Initial Issue Revised Vcc Range 4.5~5.5V => 2.7~5.5V Revised ISB1 Adding PKG type : skinny P-DIP

LY6264

Abstract: ly626416
Contextual Info:  LY626416 64K X 16 BIT LOW POWER CMOS SRAM Rev. 1.5 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 Rev. 1.5 Description Initial Issue Revised typos in page 1,4,5 35ns to 45ns Added ISB1 /IDR values when TA = 25℃ and TA = 40℃

Contextual Info: LY626416 64K X 16 BIT LOW POWER CMOS SRAM Rev. 1.7 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 Rev. 1.5 Rev. 1.6 Rev. 1.7 Description Initial Issue Revised typos in page 1,4,5 35ns to 45ns Added ISB1 /IDR values when TA = 25℃ and TA = 40℃

LY6264

Contextual Info: LY6264 8K X 8 BIT LOW POWER CMOS SRAM Rev. 2.4 FEATURES GENERAL DESCRIPTION „ Fast access time : 35/55/70ns „ Low power consumption: Operating current : 20/15/10mA TYP. Standby current : 1 A (TYP.) LL-version „ Single 2.7~5.5V power supply „ All inputs and outputs TTL compatible

LY62W128

Contextual Info: 第 1 頁，共 3 頁 Page:1/3 Update: May 22,2015 Low Power SRAM Density 64K 256K Configuration 8K x 8 32K × 8 Chip Select Dual CE Control CE#,CE2 Single CE Control (CE#) Power Supply 2.7V~5.5V 2.7V~5.5V 4.5V~5.5V 2.7V~3.6V 128K × 8 Dual CE Control (CE#, CE2)

ly62w6416

Abstract: LY6264
Contextual Info:  LY62W6416 64K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Description Initial Issue Deleted SL grade Revised FEATURES & ORDERING INFORMATION Lead free and green package available to Green package available Added packing type in ORDERING INFORMATION