M62BL7S Search Results

G175

Abstract: 234T0 82439HX CH340
Contextual Info: INTEL 430HX PCISET 82439HX SYSTEM CONTROLLER TXC • ■ ■ ■ ■ Optional Error Checking and Correction (ECC) Supports All 3V Pentium Processors Dual Processor Support PCI 2.1 Compliant Integrated Second-Level Cache Controller — — — — — —

apic - s03

Contextual Info: PENTIUM PROCESSOR WITH MMX TECHNOLOGY Maximum Operating Frequency iCOMP® Index 2.0 Rating 166 MHz 200 MHz 233 MHz 160 182 203 NOTE: Contact Intel Corporation for more information about iCOMP® Index 2.Q ratings. • Support for MMX™ Technology ■ Enhanced CMOS Silicon Technology

intel 80c186

Contextual Info: C0RP UP/PRPHLS 44E D B 4Ö2L17S OlOMflbO 5 BIITL1 . , P i l H O G Ä M ? T - 4 ^ - 1 q - /s~ 80C186 CHMOS HIGH INTEGRATION 16-BIT MICROPROCESSOR • Operation Modes Include: — Enhanced Mode Which Has — DRAM Refresh Control Unit — Power-Save Mode

LT1667

Abstract: LT1665 CA10 A058 dk 300 a008 82360SL LCD CMC 116 L01 2164 intel INTEL 82360 CD 2399 GP A049 crystal
Contextual Info: 5bE ]> • 4ÔSbl7S D i n o S M E34 « I T L 1 up/prpHLS irrte* Intel386 CORP SL MICROPROCESSOR SuperSet INTEL 'T~-(4c\ 1 7 -3 ^ Highly-Integrated Static Intel386™ SL Microprocessor Complete ISA Peripheral Subsystem System-Wide Power Management Static lntel386TM SL CPU

Contextual Info: in te i 28F016SV 16-MBIT 1 MBIT x 16,2 MBIT x 8 FlashFileTM MEMORY SmartVoltage Technology — User-Selectable 3.3V or 5V Vqc - U ser-Selectable 5V or 12V Vpp 65 ns Access Time 1 Million Erase Cycles per Block 30.8 MB/sec Burst Write Transfer Rate 0.48 MB/sec Sustainable Write Transfer

Contextual Info: intel. APPENDIX C REGISTERS This appendix provides reference information about the device registers. Table C -l lists the mod­ ules and major components of the device with their related configuration and status registers. Ta­ ble C-2 lists the registers, arranged alphabetically by mnemonic, along with their names,

Contextual Info: 80960H A/H D/HT in te i 1.0 ABOUT THIS DOCUMENT This document describes the parametric perfor­ mance of Intel’s 80960Hx embedded superscalar microprocessors. Detailed descriptions for functional topics — other than parametric performance — are published in the i9 6 P H x M icroprocessor User’s

01ag

Abstract: ML616
Contextual Info: in te l CHAPTER 3 INSTRUCTION SET REFERENCE This chapter describes the complete Intel Architecture instruction set, including the integer, floating-point, MMX technology, and system instructions. The instruction descriptions are arranged in alphabetical order. For each instruction, the forms are given for each operand combi­

82371SB

Contextual Info: intei PRELIMINARY 82371FB PIIX AND 82371 SB (PIIX3) PCI ISA IDE XCELERATOR — Independently Programmable for Edge/Level Sensitivity Bridge Between the PCI Bus and ISA Bus PCI and ISA Master/Slave Interface — PCI from 25-33 MHz — ISA from 7.5-8.33 MHz

Contextual Info: SbE J> m in te i 4fl2bl7S QllbbMM GOT H I T L l INTEL CORP UP/PRPHLS "“p M 0! \^' fyj> 87C58/80C58 • ■ ■ ■ ■ ■ ■ ■ ■ High Performance CHMOS EPROM Low Voltage Operation (-L only) Three 16-Bit Timer/Counters Programmable Clock Out Up/Down Timer/Counter