MAI61 Search Results

Contextual Info: LS TTL DN74LS Series DN74LS107 D N 7 4 LS 107 Dual J-K Flip-Flops with Reset • Description P-1 DN74LS107 contains two negative-edge triggered J-K flipflop circuits, each with independent clock-CP, J, K, and direct-coupled reset input terminals. ■ Features

Contextual Info: LS TTL DN74LS Series DN74LS138 DN74LS138 3 -lin e to 8 -lin e Decoders / Demultiplexers • Description P-2 DN74LS138 is a 3-bit decimal to octal decoder/demulti­ plexer with enable inputs. Features Three types of enable inputs Quaternary to hexadecimal decoder/demultiplexer capa­

Contextual Info: L S T T L DN74LS Series DN74LS30 DN74LS30 8 - input Positive NAND Gates • Description P-1 DN74LS30 contains one 8-input positive isolation NAND gate circuit. ■ Features • Low power consumption P,j = 2.5mW typical • High speed (tpd = 1 Ins typical)

JK flip flop IC

Contextual Info: LS TTL DN74LS Series DN74LS113 DN74LS113 l^7^iS 3 Dual J-K Negative Edge-Triggered Flip-Flops with Set) • Description DN74LS113 contains two negative-edge triggered J-K flipflop circuits, each with independent clock-CP, J, K, and direct-coupled set input terminals.

Contextual Info: LS TTL DN74LS Series DN74LS112 D N 7 4 L S 1 1 2 Dual J-K Negative Edge-Triggered Flip-Flops with Set and Reset • Description P-2 DN74LS112 contains two negative-edge triggered J-K flipflop circuits, each with independent clock-CP, J, K, and direct-coupled set and reset input terminals.