MARCH Search Results

Contextual Info: TIBPAL22V10-20M HIGH-PERFORMANCE IMPACT-X PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPSQ12A - D3523, JUNE 1 9 9 0 -R E V IS E D MARCH 1992 JT P A C K A G E Second-Generation PLD Architecture TO P V IE W High-Performance Operation: fmax (External Feedback). . . 33.3 MHz

Contextual Info: 54AC11032, 74AC11032 QUADRUPLE 2-INPUT POSITIVE-OR GATES TI0060— D2957, JULY 1987— REVISED MARCH 1990 54A C 11032 . . . J PACKAGE 74A C 11032 . . . D OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout TOP VIEW • Center-Pin V c c and GND Configurations to

LVC244

Contextual Info: I SN74LVC241 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SGAS343 - MARCH 1994 DB, DW, OR PW PACKAGE TOP VIEW E P IC (Enhanced-Performance Implanted CMOS) Submicron Process Typical V q lp (Output Ground Bounce) < 0.8 V at Vc c = 3.3 V, TA = 25°C Typical V q HV (Output V qh Undershoot)

Contextual Info: TL16C550C ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL SLLS177B- MARCH 1994 - REVISED MARCH 1996 • Programmable Auto-RTS and Auto-CTS • In Auto-CTS Mode, CTS Controls Transmitter • In Auto-RTS Mode, RCV FIFO Contents and Threshold Control RTS

Contextual Info: SN74ALS233B 16x5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SCAS253 - MARCH 1990 - REVISED JUNE 1992 • Independent Asychronous Inputs and Outputs DW OR N PACKAGE TOP VIEW • 16 Words by 5 Bits OE [ 1 FULL-1 [ 2 • Data Rates From 0 to 40 MHz • Fall-Through Ti me. . . 14 ns Typ

74283 IC pin diagram

Abstract: IC 74283 74283 IC 8 bit pin diagram
Contextual Info: SN54283, SN54LS283, SN54S283, SN74283, SN 74LS283, SN74S283 4 BIT BINARY FU LL AD DERS W ITH FA S T CARRY OCTOBEH 1976 - REVISED MARCH 1988 S N 5 4 2 8 3 , S N 5 4 L S 2 8 3 . . . J OR W PAC KA G E S N 5 4 S 2 8 3 . . . J P AC K A G E S N 7 4 2 8 3 . . . N P AC K A G E

Contextual Info: 74ACT11648 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS _ SCAS115- D3456, MARCH 1990-REVISEDAPRIL 1933 Inputs Are TTL-Voltage Compatible Independent Registers A and B Buses Multiplexed Real-Time and Stored Data Inverting Data Paths

logic diagram of 7432

Abstract: Texas Instruments TTL 7432
Contextual Info: SN5432, SN 54LS32, SN54S32. SN7432, SN74LS32, SN74S32 QUADRUPLE 2-INPUT POSITIVE-OR GATES DECEMBER 1983-REVISED MARCH 1988 Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs • SN 5432. SN 54LS32, SN 54S 32 . . . J OR W PACKAGE

F251B

Abstract: DFS06
Contextual Info: SN54F251B, SN74F251B 1-0F-8 DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS SDFS066A - MARCH 1987 - R EVISED O CTO BER 1993 3-State Versions of SN54F151B and SN74F151B 3-State Outputs Interface Directly With System Bus Performs Parallel-to-Serial Conversion

Contextual Info: SN54F20, SN74F20 DUAL 4-INPUT POSITIVE-NAND GATES D2932, MARCH 1987-REVISED JANUARY 1989 • Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs S N 5 4 F 2 0 . . . J PACKAGE S N 7 4 F 2 0 . . . 0 OR N PACKAGE

2SC 2320

Abstract: SCAS04QA-P3110
Contextual Info: 54ACT11253,74ACT11253 DUAL 1-0F-4 DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS SCAS040A - D3110, MARCH 1988 - REVISED APRIL 1993 * Inputs Are TTL-Voltage Compatible 54ACT11253 . . . J PACKAGE 74ACT11253 . . . D OH N PACKAGE TOP VIEW * 3-State Version of'ACT11153

Contextual Info: SN54ALS11A, SN54AS11, SN74ALS11A, SN74AS11 TRIPLE 3-INPUT POSITIVE-AND GATES SDAS009C - MARCH 1984 - REVISED DECEMBER 1994 • Package Options Include Plastic Small-Outline D Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

SL 2128 dip 8

Contextual Info: TISP7Ö72F3, TISP7082F3 TRIPLE SYMMETRICAL TRANSIENT VOLTAGE SUPPRESSORS SLPSEI5 - MARCH I9M - REVISED SEPTEMBER ¡994 TELECOMMUNICATION SYSTEM SECONDARY PROTECTION • lon-lmplanted Breakdown Region Precise and Stable Voltage Low Voltage Overshoot under Surge

sn74f160

Abstract: SN54F160
Contextual Info: SN 54F160A, SN 54F162A, SN 74F160A, SN 74F162A SYNCHRONOUS 4-BIT DECADE COUNTERS D2932, MARCH 1987-REVISED JANUARY 1989 • Internal Look-Ahead for Fast Counting • Carry O utput fo r n-Bit Cascading • Fully Synchronous Operation for Counting • Package Options Include Plastic "Sm all

Contextual Info: SN74LVC137 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER WITH ADDRESS LATCHES SCAS340 - MARCH 1994 » EPIC Enhanced-Performance Implanted CMOS Submicron Process • Typical V o lp (Output Ground Bounce) D, DB, OR PW PACKAGE (TOP VIEW) A[ B[ c[ Ü2A [ S2B[ G1[

Contextual Info: DS3680 QUAD TELEPHONE RELAY DRIVER SLRS014C - MARCH 1986 - REVISED SEPTEMBER 1995 Designed for -52-V Battery Operation D OR N PACKAGE TOP VIEW 50-mA Output Current Capability Input Compatible With TTL and CMOS Direct Replacement for National DS3680 and Fairchild mA3680

SN64HC

Contextual Info: SNS4HCT651, SN54HCT652. SN74HCT651. SN74HCT652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS D2B04, MARCH 19B4-REVISED SEPTEMBER 1987 Inputs are TTL-Voltage Compatible S N 6 4 H C T 6 6 1 , S N 6 4 H C T 6 6 2 . . . J T PACKAGE S N 7 4 H C T 6 6 1 . S N 7 4 H C T 6 6 2 . . . O W OR N T PACKAGE

Contextual Info: SN74F161A SYNCHRONOUS 4-BIT BINARY COUNTER SDFS056A - D2932, MARCH 19B7-REVISED OCTOBER 1993 • Internal Look-Ahead Circuitry for Fast Counting • Carry Output for N-Bit Cascading D OR N PACKAGE TOP VIEW • Fully Synchronous Operation for Counting • Package Options Include Plastic

ABT16374A

Contextual Info: SN54ABT16374A, SN74ABT16374A 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS MARCH 1993-R EV IS ED JULY 1993 Members of the Texas Instruments Widebus Family State-of-the-Art EPIC-HB" BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per

Contextual Info: SN54HC832, SN74HC832 HEX 2-INPUT OR DRIVERS D 2804, MARCH 1 9 8 4 -R E V IS E D SEPTEM BER 1987 SN 54H C 832 . . . J PACKAGE SN 7 4 H C 8 3 2 . . . D W O R N P A C K A G E High-Current Outputs Can Drive Up to 15 LSTTL Loads TO P V IEW Package Options Include Plastic "Small

74AC11827

Contextual Info: 54AC11827, 74AC11827 10-BIT BUFFERS/BUS DRIVERS WITH 3-STATE OUTPUTS TI0155— 0 3 3 7 9 . NOVEMBER 1989— REVISED MARCH 1990 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers 54AC11827 . . . JT PACKAGE 74AC11827 . . . DW OR NT PACKAGE TOP VIEW

TLC2425

Abstract: TLE24251
Contextual Info: TLE2425, TLE2425Y PRECISION VIRTUAL GROUNDS SLOSD65B - MARCH 1991 - REVISED AUGUST 1995 Excellent Regulation Characteristics - Output Regulation -4 5 nV Typ at l0 = 0 to -1 0 mA +15 nV Typ at Iq - 0 to +10 mA - Input Regulation = 1.5 ¿iV/V Typ Low-lmpedance Output. . . 0.007512 Tÿp

Contextual Info: I SN74LVC158 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER SCAS342 - MARCH 1994 D, DB, OR PW PACKAGE TOP VIEW EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Typical V q l p (Output Ground Bounce) < 0.8 V at Vc c = 3.3 V, TA = 25°C

IC 7422

Abstract: 7422 74LS22D as 5422 T3228
Contextual Info: SN5422, SN 54LS22, SN54S22, S N 7422 , S N 74 LS 2 2 , SN 74S22 D U A L 4-INPUT POSITIVE N A N D G A TES W ITH O P EN C O LLEC TO R O U TPU TS DECEMBER 1983 - REVISED MARCH 19B8 Package Options Include Plastic "Small Outline” Packages, Ceramic Chip Carriers