MARKING 1CL Search Results

B12 GDM

Abstract: BYS045 GENERAL SEMICONDUCTOR MARKING SJ SMA s104 68A BYS-045 kvp 62a GENERAL SEMICONDUCTOR MARKING mJ SMA ED BYS209 S4 68A S104 8a
Contextual Info: PDD Marking Vishay General Semiconductor PDD Marking AXIAL MARKING Cathode Band Polarity GP15M 0621X Cathode Band Part Number Logo/Date Code Polarity SB340 0621X Part Number/ Date Code/Logo DATE CODE DATE CODE 06 21 X 06 21 X Factory Designator DO-204AC/ DO-204AL

GENERAL SEMICONDUCTOR MARKING mJ SMA ED

Abstract: kvp 62a kvp 82a GFM 51A S4 68A GENERAL SEMICONDUCTOR MARKING SJ SMA 6V8C BFM 62A kvp 75a GFM 16A
Contextual Info: PPD Marking Vishay Semiconductors formerly General Semiconductor Axial Marking GS Part Number Cathode Band GP15M 0308 GS Part Number 1N4005 GP 0308 GP15M Logo/Date Code GS Logo Subject to Change Polarity Cathode Band 1N4005/Logo (GS Logo Subject to Change)

Contextual Info: M ir -r a r n iS J I ^ MT2D T 132 e, MT4D232 B, MT8D432 B 1, 2, 4 MEG X 32 DRAM MODULES 1,2, 4 MEG X 32 DRAM MODULE 4, 8, 16 MEGABYTE, 5V, BURST EDO FEATURES OPTIONS PIN ASSIGNMENT (Front View) 72-Pin SIMM (DD-11) (DD-9) (DD-8) (DD-3) MARKING • Timing 52ns access; 15ns cycle

Contextual Info: - PRELIMINARYD ecem ber 1995 Edition 2.1 FUJITSU _ P R O D U C T P R O F IL E S H E E T : MB81G83222-010/-012/-015 CMOS 2 X 128K X 3 2 SYNCHRONOUS GRAM CMOS 2 BANKS OF 131,072-WORDS x 32-BIT SYNCHRONOUS GRAPHIC RANDOM ACCESS MEMORY Marking side The Fujitsu MB81G83222 is a CMOS Synchronous Graphic Random Access Memory

Contextual Info: 2 MEG x 8 EDO DRAM M IC R O N HRAM MT4LC2M8E7 MT4C2M8E7 U n M IV I FEATURES PIN ASSIGNMENT (Top View OPTIONS 28-Pin SOJ (DA-3) Vcc [ 1* DÛ1 [ 2. DQ2¿ 3 003 r 4 DQ4 5 WE# C 6 RAS# C 7 NCC 3 AIO L 9 A0 L 10 A1 C t t A2 12 A3 t 13 Vcc [ 14 MARKING • Voltages

MT4LC2M8E7

Contextual Info: 2 MEG x 8 EDO DRAM l^ lld R O N H P AM MT4LC2M8E7 MT4C2M8E7 U n M IV I FEATURES PIN ASSIGNMENT Top View OPTIONS 28-Pin SOJ (DA-3) 1• Vcc DQ1 c 2 DQ2C 3 □03 £ 4 DQ4C 5 WE# C 6 RAS# C 7 NCC 8 A 10L 9 A0 C 10 A l C 11 A2C 12 A3 13 Vcc 14 MARKING • Voltages

Contextual Info: SN74F112 DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET SDFS048A – D2932, MARCH 1987 – REVISED OCTOBER 1993 • D OR N PACKAGE TOP VIEW Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs 1CLK 1K

Contextual Info: SN74AUC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCES483A – AUGUST 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 2CLR 3 4 12 2D 5 10 2PRE 9 2Q 11 2CLK 6 7 8 2Q • • • • • 1D 1CLK 1PRE 1Q 1Q 1CLR •

Contextual Info: SUNCON Aluminum Electrolytic Type / Surface Mount Type g 3. 2. 5 S | CO 3 • 10 5 t!, 2,000 to 5,000hrs. • Solvent proof within 2 minutes m a3 CD o • Specifications Items CE-BE CE-BD CE-BS i si & i L U 1Cl FIH Series o > ■§ 5 % Condition Rated volta ge

Contextual Info: SN74F112 DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET SDFS048A – D2932, MARCH 1987 – REVISED OCTOBER 1993 • D OR N PACKAGE TOP VIEW Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs 1CLK 1K

Contextual Info: SN54AHCT74, SN74AHCT74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCLS263N – DECEMBER 1995 – REVISED JULY 2003 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D 2CLK 2PRE 2Q 2Q 1D 1CLK 1PRE 1Q 1Q 14 1D 1 2 13 2CLR 3 12 2D 4 11 2CLK 5 10 2PRE

Contextual Info: SN54LV123A, SN74LV123A DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS SCLS393O − APRIL 1998 − REVISED OCTOBER 2005 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 1Rext/Cext 1Cext 1Q 2Q 2CLR 2B 2A 1B 1CLR 1Q 2Q 2Cext 2Rext/Cext 1 16

Contextual Info: SN54LV123A, SN74LV123A DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS SCLS393O − APRIL 1998 − REVISED OCTOBER 2005 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 1Rext/Cext 1Cext 1Q 2Q 2CLR 2B 2A 1B 1CLR 1Q 2Q 2Cext 2Rext/Cext 1 16

Contextual Info: SN54LVC74A, SN74LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET www.ti.com SCAS287S – JANUARY 1993 – REVISED MAY 2005 • 3 12 4 11 5 10 6 9 7 8 1D 1CLK 1PRE 1Q 1Q 1 14 1D VCC 2CLR 2D 2CLK 2PRE 2Q 2Q SN54LVC74A . . . FK PACKAGE

A115-A

Abstract: C101 SN54AHCT74 SN74AHCT74 hb74
Contextual Info: SN54AHCT74, SN74AHCT74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCLS263M – DECEMBER 1995 – REVISED SEPTEMBER 2002 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D 2CLK 2PRE 2Q 2Q 1D 1CLK 1PRE 1Q 1Q 14 1D 1 2 13 2CLR 3 12 2D 4 11 2CLK 5 10 2PRE

hb74

Contextual Info: SN54AHCT74, SN74AHCT74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCLS263L – DECEMBER 1995 – REVISED APRIL 2002 1CLR 1D 1CLK 1PRE 1Q 1Q GND description The ’AHCT74 dual positive-edge-triggered devices are D-type flip-flops.

A115-A

Abstract: C101 SN74AUC74 SN74AUC74RGYR
Contextual Info: SN74AUC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCES483 – AUGUST 2003 D 1D 1CLK 1PRE 1Q 1Q VCC 1 14 2 13 2CLR 3 12 2D 4 11 2CLK 5 10 2PRE 9 2Q 6 7 8 2Q D D D D D 1CLR D RGY PACKAGE TOP VIEW Optimized for 1.8-V Operation and Is 3.6-V

Contextual Info: SN54LVC74A, SN74LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET www.ti.com SCAS287S – JANUARY 1993 – REVISED MAY 2005 • 3 12 4 11 5 10 6 9 7 8 1D 1CLK 1PRE 1Q 1Q 1 14 1D VCC 2CLR 2D 2CLK 2PRE 2Q 2Q SN54LVC74A . . . FK PACKAGE

LCV74A

Contextual Info: SN54LVC74A, SN74LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS287M – JANUARY 1993 – REVISED MARCH 2002 D 1CLR 1D 1CLK 1PRE 1Q 1Q GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D 2CLK 2PRE 2Q 2Q SN54LVC74A . . . FK PACKAGE

LCV74A

Abstract: LVC74A
Contextual Info: SN54LVC74A, SN74LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS287N – JANUARY 1993 – REVISED JULY 2002 D D SN54LVC74A . . . J OR W PACKAGE SN74LVC74A . . . D, DB, NS, OR PW PACKAGE TOP VIEW 1CLR 1D 1CLK 1PRE 1Q 1Q GND

LC74A

Contextual Info: SN54LVC74A, SN74LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS287O – JANUARY 1993 – REVISED AUGUST 2002 3 12 4 11 5 10 6 9 7 8 1D 1CLK 1PRE 1Q 1Q 14 13 2CLR 3 12 2D 4 11 2CLK GND 10 2PRE 9 2Q 5 6 7 8 1CLK NC 1PRE NC 1Q

Contextual Info: SN74AUC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCES483A – AUGUST 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 2CLR 3 4 12 2D 5 10 2PRE 9 2Q 11 2CLK 6 7 8 2Q • • • • • 1D 1CLK 1PRE 1Q 1Q 1CLR •

Contextual Info: SN74AUC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCES483A – AUGUST 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 2CLR 3 4 12 2D 5 10 2PRE 9 2Q 11 2CLK 6 7 8 2Q • • • • • 1D 1CLK 1PRE 1Q 1Q 1CLR •

Contextual Info: SN74AUC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCES483A – AUGUST 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 2CLR 3 4 12 2D 5 10 2PRE 9 2Q 11 2CLK 6 7 8 2Q • • • • • 1D 1CLK 1PRE 1Q 1Q 1CLR •