MARKING CODE 8 LEAD SOIC PACKAGE Search Results

intersil DATE CODE MARKING

Contextual Info: U401/SST401 Series Ordering and Part Marking Information 3/22/11 SUBJECT: U401/SST401 Series Ordering and Part Marking Information The U401/SST401 Series Dual N-Channel JFET Amplifiers are offered in a TO-71, 6 lead package and includes the following part numbers: U401, U402, U403, U404, U405, U406

marking codes fairchild

Abstract: FAIRCHILD SEMICONDUCTOR PRODUCT MARKING CODES national marking code 8 soic 24C02 code example assembly Fairchild 24C02 NATIONAL SEMICONDUCTOR MARKING CODE TSSOP 24C02 national M08A FZ83TT NM24C02LMT8
Contextual Info: Non-Volatile Memory - EEPROM Physical Dimensions Contents Tape and Reel . 2 Part Marking . 3 Package Outlines M08A .

93c46ln

Abstract: 93s46 eprom marking codes fairchild 24U02 93S46 eeprom FAIRCHILD SEMICONDUCTOR PRODUCT MARKING CODES F46L 24C02 code example assembly 93S46 24C02LN
Contextual Info: Non-Volatile Memory - EEPROM Physical Dimensions Contents Tape and Reel . 2 Part Marking . 3 Package Outlines M08A .

5.2V Zener Diode

Abstract: IRS21064PBF IRS21064 com marking
Contextual Info: Data Sheet No. PD60241 PRELIMINARY DATASHEET IRS2106 4 D(S)PbF HIGH AND LOW SIDE DRIVER Packages Features • • • • • • • • • Floating channel designed for bootstrap operation Fully operational to +600V Tolerant to negative transient voltage – dV/dt immune

PD60246

Contextual Info: Data Sheet No. PD60246 PR EL I MI N A R Y IRS2106 4 (S) & (PbF) HIGH AND LOW SIDE DRIVER Features • Floating channel designed for bootstrap operation • • • • • • • • Packages Fully operational to +600V Tolerant to negative transient voltage

MOSFET 2302

Abstract: PD60260 marking MDt
Contextual Info: Data Sheet No. PD60260 PRELIMINARY IRS2108 4 (S) PbF Features HALF-BRIDGE DRIVER • Floating channel designed for bootstrap operation Fully operational to +600V Packages Tolerant to negative transient voltage dV/dt immune 14-Lead SOIC 8-Lead SOIC • Gate drive supply range from 10 to 20V

IR2184 application notes

Contextual Info: Data Sheet No. PD60262 PRELIMINARY IRS2181 4 (S)PbF HIGH AND LOW SIDE DRIVER Features • Floating channel designed for bootstrap operation • • • • • • • • Packages Fully operational to +600V Tolerant to negative transient voltage dV/dt immune

irs2183 application note

Abstract: irs21834s IRS21834PbF IRS21834PBF application
Contextual Info: PRELIMINARY Data Sheet No. PD60265 IRS2183 4 (S)PbF HALF-BRIDGE DRIVER Features • Floating channel designed for bootstrap operation • • • • • • • • Packages Fully operational to +600V Tolerant to negative transient voltage dV/dt immune Gate drive supply range from 10 to 20V

irs2183 application note

Abstract: IR2184 application notes IR21844 APPLICATION NOTE irs2184 and power mosfet IRS2184S IRS21844PBF IR2184 APPLICATION NOTE irs2184 marking code HO IRS2184PBF
Contextual Info: PRELIMINARY Data Sheet No. PD60252 IRS2184 4 (S)PbF HALF-BRIDGE DRIVER Features • Floating channel designed for bootstrap operation • • • • • • • • Packages Fully operational to +600V Tolerant to negative transient voltage dV/dt immune Gate drive supply range from 10 to 20V

Contextual Info: Nichrome Resistor Networks on Ceramic Substrates Models 664, 667, 668 • Isolated and bussed circuits • Thin film resistor network • 0.150” SOIC packages  

BI 668

Abstract: mil-std-202 method 215 A1002 a1002a
Contextual Info: Nichrome Resistor Networks on Ceramic Substrates Models 664, 667, 668 • Isolated and bussed circuits • Thin film resistor network • 0.150” SOIC packages  

Contextual Info: Nichrome Resistor Networks on Ceramic Substrates Models 664, 667, 668 • Isolated and bussed circuits • Thin film resistor network • 0.150” SOIC packages  

BI 668

Abstract: marking 668 51R0 MIL-R-83401
Contextual Info: MODELS 664, 667, 668 Isolated and bussed circuits Thin film resistor network 0.150” SOIC packages RoHS compliant available FEATURES Precision Nichrome Resistors on Ceramic Passivation coating provides protection in humid environments Excellent frequency response

Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 26-Aug-2013 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) UCC2807D-1 ACTIVE SOIC D 8 75

UNITRODE UC2844

Abstract: UC3842AD UC2843A-Q1
Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 4-Apr-2014 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) 5962-8670405PA ACTIVE CDIP

IR2106 APPLICATION NOTE

Abstract: ir2106pbf ir2106s datasheet IRFBC30 IR2106 IR21064 IR21064S IR2106S IRFBC20 IRFBC40
Contextual Info: Data Sheet No. PD60162 Rev. W IR2106 4 (S) & (PbF) HIGH AND LOW SIDE DRIVER Features • Floating channel designed for bootstrap operation • • • • • • • • Packages Fully operational to +600V Tolerant to negative transient voltage dV/dt immune

IR2106 APPLICATION NOTE

Abstract: IR2106S
Contextual Info: Data Sheet No. PD60162 Rev. W IR2106 4 (S) & (PbF) HIGH AND LOW SIDE DRIVER Features • Floating channel designed for bootstrap operation • • • • • • • • Packages Fully operational to +600V Tolerant to negative transient voltage dV/dt immune

uc3843an

Abstract: uc3845a UC2843A-Q1
Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 31-May-2014 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) 5962-8670405PA ACTIVE CDIP

Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 17-May-2014 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) 5962-9451301MPA ACTIVE CDIP

UC3842AD

Abstract: UC2842ADW UC2843A-Q1
Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) 5962-8670405PA ACTIVE CDIP JG

hel04

Abstract: XEL04 e104
Contextual Info: SY10EL04 SY100EL04 FINAL 2-INPUT AND/NAND FEATURES • ■ ■ ■ DESCRIPTION 240ps propagation delay High bandwidth output transitions Internal 75KΩ input pull-down resistors Available in 8-pin SOIC package The SY10/100EL04 are 2-input AND/NAND gates.

UC1844AJ

Abstract: UC2843A-Q1
Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 26-Aug-2013 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) 5962-8670405PA ACTIVE CDIP JG

Contextual Info: TLC5615C, TLC5615I www.ti.com SLAS142E – OCTOBER 1996 – REVISED JUNE 2007 10-BIT DIGITAL-TO-ANALOG CONVERTERS FEATURES • • • • • • • • • • • 10-Bit CMOS Voltage Output DAC in an 8-Terminal Package 5V Single Supply Operation 3-Wire Serial Interface

HEL01

Contextual Info: SY10EL01 SY100EL01 FINAL 4-INPUT OR/NOR FEATURES • ■ ■ ■ DESCRIPTION 230ps propagation delay High bandwidth output transitions Internal 75KΩ input pull-down resistors Available in 8-pin SOIC package The SY10/100EL01 are 4-input OR/NOR gates. These