MC100EP Search Results

AZ100EP16VS

Abstract: AZ100EP16VST AZ10EP16VS AZ10EP16VST MC100EP16VS NC 1350
Contextual Info: ARIZONA MICROTEK, INC. AZ10EP16VS AZ100EP16VS ECL/PECL Differential Receiver with Variable Output Swing FEATURES • • • • • Silicon-Germanium for High Speed Operation 150ps Typical Propagation Delay AZ100EP16VS Functionally Equivalent to ON Semiconductor MC100EP16VS

KPT25

Abstract: EPT25 MC100EPT25 MC100EPT25D MC100EPT25DR2 MC100EPT25DT MC100EPT25DTR2 KA25 kpt25 alyw
Contextual Info: MC100EPT25 −3.3V / −5V Differential ECL to +3.3V LVTTL Translator The MC100EPT25 is a Differential ECL to LVTTL translator. This device requires +3.3 V, -3.3 V to -5.2 V, and ground. The small outline 8-lead package and the single gate of the EPT25 make it ideal

LQFP32

Abstract: LQFP-32 MC100 MC100EPT622 MC100EPT622FA MC100EPT622FAR2
Contextual Info: MC100EPT622 3.3V LVTTL/LVCMOS to LVPECL Translator The MC100EPT622 is a 10- Bit LVTTL/LVCMOS to LVPECL translator. Because LVPECL Positive ECL levels are used only +3.3 V and ground are required. The device has an OR- ed enable input which can accept either LVPECL (ENPECL) or TTL/LVCMOS inputs

MC100EP90

Abstract: MC100EP90DT MC100EP90DTR2 MC10EP90 MC10EP90DT MC10EP90DTR2
Contextual Info: MC10EP90, MC100EP90 -3.3V / -5VĄTriple ECL Input to LVPECL/PECL Output Translator The MC10/100EP90 is a TRIPLE ECL TO LVPECL/PECL translator. The device receives differential LVECL or ECL signals and translates them to differential LVPECL or PECL output signals.

KEP05

Abstract: HEP05 MC100EP05 MC10EP05
Contextual Info: MC10EP05, MC100EP05 3.3V / 5VĄECL 2-Input Differential AND/NAND The MC10/100EP05 is a 2–input differential AND/NAND gate. The device is functionally equivalent to the EL05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP05 is ideal for applications requiring the fastest AC performance

EP809

Abstract: MC100EP809 MC100EP809FA MC100EP809FAG MC100 SY89809L MC100EP809FAR2 MC100EP809FAR2G
Contextual Info: MC100EP809 3.3V 1:9 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Enable http://onsemi.com Description The MC100EP809 is a low skew 1−to−9 differential clock driver, designed with clock distribution in mind, accepting two clock sources into

MC10EP016

Abstract: MC100EP016 MC10E016
Contextual Info: MC10EP016, MC100EP016 3.3V / 5V ECL 8−Bit Synchronous Binary Up Counter The MC10/100EP016 is a high−speed synchronous, presettable, cascadeable 8−bit binary counter. Architecture and operation are the same as the MC10E016 in the ECLinPS family. The counter features internal feedback to TC gated by the TCLD

EP29

Abstract: MC100EP29 MC10EP29
Contextual Info: MC10EP29, MC100EP29 3.3V / 5V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset http://onsemi.com Description The MC10/100EP29 is a dual master−slave flip−flop. The device features fully differential Data and Clock inputs as well as outputs.

LVDS100

Abstract: MC100EP16 SN65LVDS100 SN65LVDS100D SN65LVDS100DGK SN65LVDS101 SN65LVDT100 SN65LVDT100D SN65LVDT101
Contextual Info: SN65LVDS100, SN65LVDT100 SN65LVDS101, SN65LVDT101 www.ti.com SLLS516B − AUGUST 2002 − REVISED SEPTEMBER 2003 DIFFERENTIAL TRANSLATOR/REPEATER FEATURES D Designed for Signaling Rates 1 . 2 Gbps D Total Jitter < 65 ps D Low-Power Alternative for the MC100EP16

KEP16

Abstract: LVEL16 MC100EP16 MC10EP16
Contextual Info: MC10EP16, MC100EP16 3.3V / 5V ECL Differential Receiver/Driver Description http://onsemi.com MARKING DIAGRAMS* 8 8 1 SOIC−8 D SUFFIX CASE 751 1 8 8 1 Features TSSOP−8 DT SUFFIX CASE 948R • 220 ps Typical Propagation Delay • Maximum Frequency > 4 GHz Typical

MC100EP35

Abstract: EL35 HP35 KP35 MC10EP35 code KP35
Contextual Info: MC10EP35, MC100EP35 3.3V / 5V ECL JK Flip−Flop Description The MC10/100EP35 is a higher speed/low voltage version of the EL35 JK flip−flop. The J/K data enters the master portion of the flip−flop when the clock is LOW and is transferred to the slave, and

HEP58

Abstract: MC100EP58 MC10EP58
Contextual Info: MC10EP58, MC100EP58 3.3V / 5VĄECL 2:1 Multiplexer The MC10/100EP58 is a 2:1 multiplexer. The device is pin and functionally equivalent to the EL58 and LVEL58 devices. The 100 Series contains temperature compensation. • 310 ps Typical Propagation Delay • Maximum Frequency > 3 GHz Typical

MC100EP111

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Product Preview MC100EP111 Low-Voltage 1:10 Differential ECL/PECL Clock Driver The MC100EP111 is a low skew 1–to–10 differential driver, designed with clock distribution in mind. It accepts two clock sources into an input

MC100

Abstract: MC100E016 MC100EP016 MC100EP016A MC100EP016AFA MC100EP016AFAR2 25pe16
Contextual Info: MC100EP016A 3.3 VĄECL 8-Bit Synchronous Binary Up Counter The MC100EP016A is a high–speed synchronous, presettable, cascadeable 8–bit binary counter. Architecture and operation are the same as the ECLinPS family MC100E016 with higher operating speed.

EP809

Abstract: MC100EP809 MC100EP809FA MC100EP809FAR2 MC100 SY89809L
Contextual Info: MC100EP809 3.3VĄ1:9 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Enable The MC100EP809 is a low skew 1–to–9 differential clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The part is designed for use in low voltage

100EP

Abstract: EP14 MC100EP14
Contextual Info: MC100EP14 3.3V / 5V 1:5 Differential ECL/PECL/HSTL Clock Driver Description The MC100EP14 is a low skew 1−to−5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or

Contextual Info: MC10EP56, MC100EP56 3.3V / 5V ECL Dual Differential 2:1 Multiplexer Description The MC10/100EP56 is a dual, fully differential 2:1 multiplexer. The differential data path makes the device ideal for multiplexing low skew clock or other skew sensitive signals. Multiple VBB pins are

Contextual Info: MC10EP105, MC100EP105 3.3V / 5VĄECL Quad 2-Input Differential AND/NAND The MC10/100EP105 is a quad 2–input differential AND/NAND gate. Each gate is functionally equivalent to the EP05 and LVEL05 devices. With AC performance much faster than the LVEL05 device,

Contextual Info: MC100EP196B 3.3 V ECL Programmable Delay Chip With FTUNE Descriptions The MC100EP196B is a Programmable Delay Chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar

Contextual Info: MC100EP195B 3.3V ECL Programmable Delay Chip Descriptions The MC100EP195B is a Programmable Delay Chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The delay section consists of a programmable matrix of gates and

Contextual Info: MOTO RO LA °rderNumber:M R ro” Semiconductor Components M C 100EPT23 ♦ SO -8, D SUFFIX 8-LEAD PLASTIC SOIC PACKAGE CASE 751-06 ORDERING INFORMATION MC100EPT23D Product Preview D ual D iffe re n tia l LVPECL to LVTTL T ra n s la to r SOIC PIN DESCRIPTION

Contextual Info: ECL Pro ECL Pro™ SY100EP195V SY100EP195V FINAL 3.3V/5V 2.5GHz PROGRAMMABLE DELAY CHIP Micrel FEATURES • Pin-for-pin, plug-in compatible to the ON Semiconductor MC100EP195 ■ Maximum frequency > 2.5GHz ■ Programmable range: 2.2ns to 12.2ns ■ 10ps increments

MC100EP016A

Abstract: 100EP MC100 MC100E016 MC100EP016
Contextual Info: MC100EP016A 3.3 V ECL 8−Bit Synchronous Binary Up Counter Description The MC100EP016A is a high−speed synchronous, presettable, cascadeable 8−bit binary counter. Architecture and operation are the same as the ECLinPS family MC100E016 with higher operating

EP57

Abstract: MC100EP57 MC10EP57 100EP57
Contextual Info: MC10EP57, MC100EP57 3.3V / 5V ECL 4:1 Differential Multiplexer Description The MC10/100EP57 is a fully differential 4:1 multiplexer. By leaving the SEL1 line open pulled LOW via the input pulldown resistors the device can also be used as a differential 2:1 multiplexer