MCR 16 313 Search Results

Contextual Info: Z550 UART 0.5µ m Technology Mega Macrocell for Universal Asynchronous Receiver/Transmitter DESCRIPTION The Z550 UART Mega Macrocell is a featured library element in all of OKI’s 0.5µm Sea of Gates and 0.5µm Customer Structured Array families. The OKI implementation of the mega macrocell is fully compatible

Z550

Abstract: MSM13R0000 MSM98R000 UART s
Contextual Info: DATA SHEET O K I A S I C P R O D U C T S Z550 0.5 µm UART Mega Macrocell August 1996 • ■ –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––

Contextual Info: a 82C50A HARRIS S E M I C O N D U C T O R CMOS Asynchronous Communications Element August 1996 Features Description • • • • The 82C50A Asynchronous Communication Element ACE is a high performance programmable Universal Asynchro­ nous Receiver/Transmitter (UART) and Baud Rate Genera­

ST16C1450

Contextual Info: ST16C1450 ST16C1451 STARTECH An Printed June 19, 1996 Company UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER D0 26 DSR* D1 1 27 CD* D2 2 28 VCC D3 3 23 DTR* D7 8 22 RTS* RX 9 21 A0 TX 10 20 A1 CS* 11 19 A2 17 RI* INT 18 16 14 IOW* IOR* 13 GND 15 12 ST16C1450CJ28

Contextual Info: ST16C2550 STARTECH An Company Printed June 19, 1996 DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER WITH FIFOs D4 D3 D2 D1 D0 TXRDYA* VCC RIA* CDA* DSRA* CTSA* 4 3 2 1 44 43 42 41 40 D5 7 39 RESET D6 8 38 DTRB* D7 9 37 DTRA* RXB 10 36 RTSA* RXA 11 35 OPA* TXRDYB* 12

16C450CQ

Contextual Info: JSTEXAR ST16C450 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER UART GENERAL DESCRIPTION The ST16C450 is a universal asynchronous receiver and transmitter. The ST 16C450 is an improved ver­ sion ot the NS16450 UART with higher operating speed and lower access time. A programmable baud

VL16C450

Abstract: NS16450 NS16C450 ST16C2450 ST16C2450CJ44 ST16C2450CP40 WD16C450 162450-RD-1
Contextual Info: STARTECH ST16C2450 An 28? EX4RCompany Printed August 3, 1995 DUAL UNIVERSAL ASYNCHRONOUSRECEIVER/TRANSMITTER DESCRIPTION PLCC Package The ST16C2450 is a dual universal asynchronous receiverand transmitter. Independent programmable baud rate generators are provided to select transmit

ARM920T

Abstract: TAG90 141 mrc ARM processor Armv4 ARM920T rom cp15 149 StrongARM SA110 B-30 CP15 arm9tdmi
Contextual Info: ARM920T Rev 1 Technical Reference Manual Copyright 2000, 2001 ARM Limited. All rights reserved. ARM DDI 0151C ARM920T Technical Reference Manual Copyright © 2000, 2001 ARM Limited. All rights reserved. Release Information Change history Date Issue Change

ST16C650A

Contextual Info: ST16C650A ZBTEXAR UART WITH 32-BYTE FIFO’s AND INFRARED IrDA ENCODER/DECODER GENERAL DESCRIPTION The ST16C650A"’ is a universal asynchronous receiver and transmitter (UART) and is pin compatible with the ST 16C550 UART. The 650Ais an enhanced UART with 32 byte FIFOs, automatic hardware/software flow control,

ARM9TDMI

Abstract: ARM922T 141 mrc basic architecture of ARM Processors B-30 CP15
Contextual Info: ARM922T Rev 0 Technical Reference Manual Copyright 2000, 2001 ARM Limited. All rights reserved. ARM DDI 0184B ARM922T Technical Reference Manual Copyright © 2000, 2001 ARM Limited. All rights reserved. Release Information Change history Date Issue Change

VL16C450

Abstract: VL16C550 Delco 195 sorep s3607 MSR 200 VL16C550PC
Contextual Info: VLSI Tech no lo gy , in c . VL16C550 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFOs FEATURES DESCRIPTION • Fully compatible with VL16C450 ACE The VL16C550 is an asynchronous communications element ACE that is functionally equivalent to the VL16C450, and additionally incorpo­

Contextual Info: STARTECH ST16C2550 An J£* EX<IRCompany Printed August 3, 1995 DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER WITH FIFOs DESCRIPTION PLCC Package The ST 16C2550 is a dual asynchronous receiver and transmitter with 16 byte transmit and receive FIFO. Independent programmable baud rate generators are

1fg1

Abstract: 16C1552 16c1550 st16c1550
Contextual Info: ST16C1550 ST16C1551/1552 STARTECH Printed September 15, 1994 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER WITH FIFOs DESCRIPTION PLCC Package The ST16C1550/51/52 is a universal asynchronous receiver and transmitter with 16 byte transmit and receive FIFO. A programmable baud rate generator is

80C86

Abstract: CA82C59A S101 modem circuit echo CA82C84A
Contextual Info: "TUNDRA CA82C52 CMOS SERIAL CONTROLLER INTERFACE • Pin and functional compatibility with the industry standard 8252 • TTL input/output compatibility • Low power CMOS implementation • High speed - DC to 16 MHz operation • Single chip UART/BRG • Crystal or external clock input

16C1450

Abstract: 73M14 ST16C1450
Contextual Info: ST16C1450 ST16C1451 STARTECH A n 26* E X 4 R C o m p a n y Printed August 3,1995 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER ST16C1450 PLCC Package DESCRIPTION The ST16C1450/51 is a universal asynchronous re­ ceiver and transmitter. A programmable baud rate

Contextual Info: ^ STARTECH ST16C2450 An 25? EXflRCompany Printed August 3,1995 DUAL UNIVERSAL ASYNCHRONOUSRECEIVER/TRANSMITTER DESCRIPTION PLCC Package The ST16C2450 is a dual universal asynchronous receiverand transmitter. Independent programmable baud rate generators are provided to select transmit

Contextual Info: STARTECH ST16C2552 An 2g*EX4RCompany Printed August 3,1995 DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER WITH FIFOs DESCRIPTION PLCC Package The ST 16C2552 is a dual asynchronous receiver and transmitter with 16 byte transmit and receive FIFOs. Independent programmable baud rate generators are

16C2550

Contextual Info: ST16C2550 STARTECH Printed December 17, 1996 An J F EXARCompany DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER WITH FIFOs DESCRIPTION PLCC Package The ST 16C2550 is a dual asynchronous receiver and transmitter with 16 byte transmit and receive FIFO. Independent programmable baud rate generators are

INS8250

Abstract: NS16C550 NS16C552 ST16C2552 ST16C2552CJ44 ST16C2552CQ48 ST16C2552IJ44 ST16C450 ST16C550 RXB 24
Contextual Info: STARTECH ST16C2552 An Printed December 17, 1996 Company DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER WITH FIFOs D4 D3 D2 D1 D0 TXRDYA* VCC RIA* CDA* DSRA* CTSA* 4 3 2 1 44 43 42 41 40 D5 7 39 RXA D6 8 38 TXA D7 9 37 DTRA* A0 10 36 RTSA* XTAL1 11 35 MFA* GND 12 34

ST16C2550

Abstract: NS16C550 INS8250 ST16C2450 ST16C2550CJ44 ST16C2550CP40 ST16C550 ht44
Contextual Info: » STARTECH ST16C2550 Printed August 3, 1995 An 3 P EX4RCompany DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER WITH FIFOs DESCRIPTION PLCC Package The ST 16C2550 is a dual asynchronous receiver and transmitter with 16 byte transmit and receive FIFO. Independent programmable baud rate generators are

Contextual Info: CA82C52 f ÿ TU N D RA CMOS SERIAL CONTROLLER INTERFACE Pin and functional compatibility with the industry standard 8252 TTL input/output compatibility Low power CMOS implementation High speed - DC to 16 MHz operation Single chip UART/BRG Crystal or external clock input

DDI0198B

Abstract: ARM926EJ-S Implementation Guide DDI0198B thumb instruction set ARM DII 0015 DXI 0131 ARM9EJ-S ARM926EJ-S CP15 dii 0157 ARM DII 0222
Contextual Info: ARM926EJ-S Rev 0 Technical Reference Manual Copyright 2001-2002 ARM Limited. All rights reserved. ARM DDI0198B ARM926EJ-S Technical Reference Manual Copyright © 2001-2002 ARM Limited. All rights reserved. Release Information Change history Date Issue

Contextual Info: JBTEXAR ST16C2552 DUAL UART WITH 16-BYTE TRANSMIT AND RECEIVE FIFO’S DESCRIPTION The ST16C2552 2552 is a dual universal asynchronous receiver and transmitter (UART). The ST16C2552 is an improved version of the NS16C552 UART. The 2552 provides enhanced UART functions with 16 byte FIFOs,

vl16c552

Abstract: lpt port direction bit 5
Contextual Info: VLSI Tech n o lo gy , in c . VL16C552 DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO FEATURES • Three-state TTL drive for the data and control bus on each channel • IBM PC/AT -compatible • Two VL16C550 ACEs • Hardware and software compatible with VL16C452 and VL16C452B