MO-229 FOOTPRINT Search Results

30N30

Abstract: 96542B
Contextual Info: HiPerFAST IGBT IXGH30N30 IXGH30N30S vCES *C25 VCE sat 300 60 1.6 180 V A V ns Preliminary data Symbol Test Conditions VCES Tj = 25°Cto150°C 300 V vCGR ^ = 25°Cto150°C; RGE = 1 MO 300 V vGES Continuous ±20 V VGEM Transient ±30 V 60 A 30 A 120 A Maximum Ratings

Contextual Info: MO TO RO LA SC X ST RS /R F bflE D • b 3 b ? S S H DGiöfiB? SSb ■ MOTb MOTOROLA SEMICONDUCTOR TECHNICAL DATA Advance Information TMOS E-FET Power Field Effect Transistor N-Channel Enhancement-Mode Silicon Gate TMOS POWER FET 8.0 AMPERES RDS(on) = °-80 OHM

051hvh

Abstract: LTC2051HVCDD LTC2052HVHS LTC2051 LTC2051HV LTC2052 LTC2051HVIMS10
Contextual Info: LTC2051/LTC2052 Dual/Quad Zero-Drift Operational Amplifiers U FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO Maximum Offset Voltage of 3 V Maximum Offset Voltage Drift of 30nV/°C Small Footprint, Low Profile MS8/GN16 Packages Single Supply Operation: 2.7V to ±5.5V

LTC2051

Abstract: LTC2051HV LTC2052 S14 MSOP
Contextual Info: LTC2051/LTC2052 Dual/Quad Zero-Drift Operational Amplifiers U FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO Maximum Offset Voltage of 3 V Maximum Offset Voltage Drift of 30nV/°C Small Footprint, Low Profile MS8/GN16 Packages Single Supply Operation: 2.7V to ±5.5V

Contextual Info: LTC2051/LTC2052 Dual/Quad Zero-Drift Operational Amplifiers U FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO Maximum Offset Voltage of 3 V Maximum Offset Voltage Drift of 30nV/°C Small Footprint, Low Profile MS8/GN16 Packages Single Supply Operation: 2.7V to ±5.5V

LT2051

Abstract: LT20 LTC2051 LTC2051HV LTC2052 2051HV
Contextual Info: LTC2051/LTC2052 Dual/Quad Zero-Drift Operational Amplifiers U FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO Maximum Offset Voltage of 3µV Maximum Offset Voltage Drift of 30nV/°C Small Footprint, Low Profile MS8/GN16 Packages Available in 3mm x 3mm × 0.8mm DFN Package

Contextual Info: June 2012 OFF-THE-SHELF Analog, Digital & Mixed-Signal ICs, Modules, Subsystems & Instrumentation Hittite Exhibiting at MTT-S 2012! View our product demos in Montreal, June 19 to 21, 2012. Booth #1701 ADC HMC9000 Multi-GHz Quantizer 25 New Featured Products!

Contextual Info: AT6000 Series Features • • • • • • • High Performance System Speeds > 1 0 0 MHz Flip-Flop Toggle Rates > 250 MHz 1.2 ns Input Delay 3.5 ns Output Delay Thousands of Registers Cache Logic Design Complete/Partial In-System Reconfiguration No Loss of Data or Machine State

Contextual Info: FEATURES ●Efficiency up to 86% ●Wide input range 2:1 ●Operating temperature: -40°C to +85°C ●1.5KVDC isolation ●Metal shielding package ●Industry standard pinout ●MTBF>1,000,000 hours ●Good high temperature properties, can meet the industrial products technical

FA526

Abstract: MSP2206 EA-3016 PMC-2052032 CP14 CP15 MSP2200 MSP2202 EAt-11 ARM coprocessor faraday
Contextual Info: Mo nd ay ,1 MSP2200 3M ar ch ,2 00 6 10 :1 2: 34 PM MSP2200 Data Sheet Advance rtm in er In co n Multi-Service Processor Advance Issue No. 1: November 2005 Do wn l oa de d by C on te nt T ea m of Pa Data Sheet Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.

45 KW 3-phase motor weight

Contextual Info: 3G3MX2 AC Drives Born to drive machines » »O m ro n Q u a l i ty w i t h a c a p i t a l " Q " » »H i g h p ro g ra m m i n g f u n c t i o n a l i ty » » B u i l t- i n s a fe ty Harmonized motor and machine control MOTOR C O N T RO L The 3G3MX2 is specifically designed to drive

Contextual Info: AT6000 Series Features • • • • • • • High Performance System Speeds to 70 MHz Flip-Flop Toggle Rates to 250 MHz Symmetrical Architecture Thousands of Registers Flexible Busing Network Predictable Timing Delays 100% Factory-Tested Cache Logic Design

GV1 M10

Abstract: TPC842 A7 B14
Contextual Info: tlX IU N X XC5200 Field Programmable Gate Arrays August 6,1996 Version 4.01 Preliminary Product Specification Features • Fully supported by XACTstep Development System - Includes complete support for XACT-Performance™, X-BLOX™, Unified Libraries, Relationally Placed

Contextual Info: JIXILINX XC5200 Field Programmable Gate Arrays June 1, 1996 Version 4.0 Preliminary Product Specification Features • Fully supported by XACTsfep Development System - Includes complete support for XACT-Performance™, X-BLOX™, Unified Libraries, Relationally Placed

Contextual Info: £ XC5200 Field Programmable Gate Arrays x ilin x August 6,1996 Version 4.01 Preliminary Product Specification Features • Fully supported by XACTsfep Development System - Includes complete support for XACT-Performance™, X-BLOX™, Unified Libraries, Relationally Placed

gc 7137 ad

Abstract: transistor c5200 c5200 transistor TTC 5200 C5200 LC1 D18 P7 HC 148 TRANSISTOR ATIC 164 D2 44 pin
Contextual Info: £ XILINX XC5200 Series Field Programmable Gate Arrays Novem ber 5, 1998 Version 5.2 Product Specification Features - • Low-cost, register/latch rich, SRAM based reprogram m able architecture - 0.5|j.m three-layer metal CMOS process technology - 256 to 1936 logic cells (3,000 to 23,000 “gates”)

XCS200 FPGA

Contextual Info: HXILINX XC5200 Series Field Programmable Gate Arrays December 10, 1997 Version 5.0 Product Specification Features • • Low-cost, process-optimized, register/latch rich, SRAM based reprogrammable architecture - 0.5pm three-layer metal CMOS process technology

Contextual Info: Mo nd ay ,1 MSP2204 3M ar ch ,2 00 6 10 :1 3: 34 PM MSP2204 Data Sheet Advance rtm in er In co n Multiservice Processor Advance Issue No. 1: January 2006 Do wn l oa de d by C on te nt T ea m of Pa Data Sheet Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.

ATIC 164 D2 44 pin

Abstract: ATIC 164 D2 48 pin ATIC 164 D3
Contextual Info: H X IL IN X XC5200 Field Programmable Gate Arrays June 1, 1996 Version 4.0 Prelim inary Product Specification Features • • High-density family of Field-Program m able Gate Arrays (FPGAs) • Design- and process-optimized for low cost - 0.6-nm three-layer metal (TLM) process

TMS320C40

Abstract: SMJ320C40 application SMJ320C40 A7261
Contextual Info: SMJ320MCM41A SINGLE SMJ320C40 MULTICHIP MODULE SGMS719 – JUNE 1995 D D D D D D D D Performance – 40 MFLOP With 256-Megabyte / s Burst I/O Rate for 40-MHz Modules – 33 MFLOP With 211-Megabyte / s Burst I / O Rate for 33-MHz Modules – 128K x 32 Zero-Wait-State Local Memory;

STR G 8654

Abstract: A673 transistor transistor A673 transistor Bu 45080 TT 2188 mx 362-0 TRANSISTOR SMD MARKING CODE 3401 diode BZW 70-20 sfh 202 diode 3302 81a ir receiver
Contextual Info: Foreword Foreword Foreword Vorwort The information in this catalog is correct as of March 2011. Die Angaben in diesem Katalog entsprechen dem Stand März 2011. All products listed in this catalog are RoHS compliant, a fact that will be explicitly noted in the respective data sheet. For up-to-date

1736a

Abstract: xc1736 die
Contextual Info: XC3000 Logic CeU Array Family Product Specification FEATURES The LCA user logic functions and interconnections are determined by the configuration program data stored in internal static memory cells. The program can be loaded in any of several modes to accommodate various system

FEPROM

Abstract: YL41 10B60 LM 10841 7v71 10B28 U131-1-2
Contextual Info: PRELIM INARY VF1 FPGA Family B EY O N D P ER F O R M A N C E FEATURES AND BENEFITS ♦ The industry’s first Variable-Grain-Architecture enables high-density, high-performance designs for a wide range of applications — Architecture adapts to logic to enable synthesis-friendly, high-performance designs

epson FC-135 marking

Abstract: XV-3500CB j 6920a XV-8000CB 6601d toyocom tcxo metal package FC-135 MARKING TSX-3225 XV-8000LK XG-1000CB 98
Contextual Info: Crystal unit Epson Toyocom MHz RANGE CRYSTAL UNIT MINIATURE SIZE LOW PROFILE SMD FA - 238V / FA - 238 TSX - 3225 •Frequency range •Thickness •Overtone order •Applications : 12 MHz to 54 MHz : 0.6 mm Max. TSX-3225 : Fundamental : Mobile phone, Bluetooth, W-LAN