MO151 Search Results

DF2-A

Abstract: XB2H DF2E
Contextual Info: TL3M Device Triple Level 3 Mapper TXC-03453 DESCRIPTION • Maps up to three independent DS3/E3 line formats into SDH/SONET formats as follows: - DS3 to/from STM-1/TUG-3 - DS3 to/from STS-3/STS-1 - E3 to/from STM-1/TUG-3 • SDH/SONET bus access: - Byte wide drop and add buses

Contextual Info: TL3M Device Triple Level 3 Mapper TXC-03453 DESCRIPTION • Maps up to three independent DS3/E3 line formats into SDH/SONET formats as follows: - DS3 to/from STM-1/TUG-3 - DS3 to/from STS-3/STS-1 - E3 to/from STM-1/TUG-3 • SDH/SONET bus access: - Byte-wide drop and add buses

VTXP-6

Abstract: TXC-06951 g803 Motorola 0X69 TXC-06951-MB 98822
Contextual Info: VTXP-6 Device STM-1/STS-3 SDH/SONET TU/VT Processor and Cross Connect TXC-06951 DATA SHEET PRELIMINARY TXC-06951-MB, Ed. 5 March 2006 FEATURES APPLICATIONS • Supports two line ports using the standard byte wide 19.44 MHz Telecom Bus, or a single line port using the standard byte wide 77.76 MHz Telecom Bus.

CHIP EPROM AE12

Abstract: spru402 ST2328
Contextual Info: TMS320C6201 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SPRS051G – JANUARY 1997 – REVISED NOVEMBER 2000 D High-Performance Fixed-Point Digital D D D D D D Signal Processor DSP TMS320C6201 – 5-ns Instruction Cycle Time – 200-MHz Clock Rate – Eight 32-Bit Instructions/Cycle

GR-1400

Contextual Info: PHAST-12E Device Programmable, High-Performance ATM/PPP/TDM SONET/SDH Terminator for Level 12 with Enhanced Features TXC-06212 TECHNICAL OVERVIEW LINE SIDE Serial LIU Clocks The PHAST-12E is a highly integrated SONET/SDH terminator device designed for ATM cell, frame, higher order multiplexing,

TH4B

Contextual Info: PHAST-3N STM-1/STS-3/STS-3c SDH/SONET Overhead Terminator with Telecom Bus Interface TXC-06103 DATA SHEET • • • • • • • • • • • • • • • • • Bit-serial SDH/SONET line interface - Pseudo-ECL interface with clock recovery and synthesis

TUG-3

Abstract: vc-4 digital cross connect
Contextual Info: TL3M Device Triple Level 3 Mapper TXC-03453B TECHNICAL OVERVIEW Each of the three channels of the TL3M can map a DS3 line signal into an STM-1 TUG-3 or STS-3 STS-1 SPE SDH/SONET signal. An E3 signal can be mapped only into an STM-1 TUG-3. The TL3M interfaces to an STM-1 or STS-3 SDH/SONET signal

C6701

Contextual Info: TMS320C6701 FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR SPRS067E – MAY 1998 – REVISED MAY 2000 D Highest Performance Floating-Point Digital D D D D D Signal Processor DSP TMS320C6701 – 8.3-, 6.7-, 6-ns Instruction Cycle Time – 120-, 150-, 167-MHz Clock Rate

of TX6A RX6A

Abstract: RX6A tx2c transmitter RX6a 1211 TX1B TXC-06885 diode GFP AA tx6c TX5b rx5b Ethernet over SONET mapper
Contextual Info: Envoy -CE4 Device SPI-3 to Ethernet Controller TXC-06885 DATA SHEET PRODUCT PREVIEW • 4 Configurable Media Access Controllers MACs • Each MAC is configurable as 8 Fast Ethernet ports (10/100 Mbits/s) or 2 Fast Ethernet ports with extended buffers or 1 Gigabit Ethernet port (10/100/1000 Mbits/s)

Contextual Info: TL3M Device Triple Level 3 Mapper TXC-03453 TECHNICAL OVERVIEW SDH/SONET SIDE TELECOM BUS O-Bit Interfaces • Add/drop multiplexers • Digital cross connect systems • Broadband switching systems • Transmission equipment External Alarm Interfaces Drop Bus

DSLAM structure

Contextual Info: CUBIT-622 Device Multi-PHY CellBus Access Device TXC-05805 DESCRIPTION • 622 Mbit/s performance • UTOPIA Level 1/2 interface 8/16-bit with support for 64 ports • Tandem operation for two devices, supporting dual CellBus cell switching in load sharing or redundancy

Contextual Info: PHAST -12N Device STM-4/OC-12 SDH/SONET Overhead Terminator with Telecom Bus Interface TXC-06312 DESCRIPTION • Bit-serial LVPECL SDH/SONET line interface with integrated clock recovery and clock synthesis - single 622.08 Mbit/s STM-4/OC-12 signal or - four 155.52 Mbit/s STM-1/OC-3 signals

RJP 30 h1

Contextual Info: TMS320C6713B FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 D Highest-Performance Floating-Point Digital D D D D D D Signal Processor DSP : TMS320C6713B − Eight 32-Bit Instructions/Cycle − 32/64-Bit Data Word

Contextual Info: TMS320C6712D FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 D Low-Price/High-Performance Floating-Point D D D D D Digital Signal Processor DSP : TMS320C6712D − Eight 32-Bit Instructions/Cycle − 150-MHz Clock Rate

Contextual Info: SM320C6711ĆEP, SM320C6711BĆEP, SM320C6711CĆEP, SM320C6711DĆEP FLOATINGĆPOINT DIGITAL SIGNAL PROCESSORS SGUS054A − AUGUST 2004 − REVISED SEPTEMBER 2005 D Controlled Baseline D D D D D D D D L1/L2 Memory Architecture − One Assembly/Test Site, One Fabrication

352-PIN

Abstract: TMS320C6202 TMS320C6202B
Contextual Info: TMS320C6202, TMS320C6202B FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS104I - OCTOBER 1999 - REVISED MARCH 2004 D High-Performance Fixed-Point Digital D D D D D D Signal Processors DSPs - TMS320C62x - 5-, 4-, 3.33-ns Instruction Cycle Time - 200-, 250-, 300-MHz Clock Rate

c4460

Abstract: TMSC44 TMS320C40GFL Texas Instruments processor selection guide 1994 120M 336M LD31 TMS320C44 TMS320C44-50 TMS320C44-60
Contextual Info: TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 D Highest Performance Floating-Point Digital D D D D D D D D D Signal Processor DSP − TMS320C44-60: 33-ns Instruction Cycle Time, 330 MOPS, 60 MFLOPS, 30 MIPS, 336M Bytes/s

Contextual Info: TMS320C6701 FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR SPRS067F − MAY 1998 − REVISED MARCH 2004 D Highest Performance Floating-Point Digital D D D D D Signal Processor DSP TMS320C6701 − 8.3-, 6.7-, 6-ns Instruction Cycle Time − 120-, 150-, 167-MHz Clock Rate

Contextual Info: TMS320C6713B FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 D Highest-Performance Floating-Point Digital D D D D D D Signal Processor DSP : TMS320C6713B − Eight 32-Bit Instructions/Cycle − 32/64-Bit Data Word

Contextual Info: SM320C6701ĆEP, SM320C6701MECHĆEP FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR SGUS042A − MAY 1998 − REVISED APRIL 2004 D Controlled Baseline D D D D D D D D 1M-Bit On-Chip SRAM − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance up to

EAXXX

Contextual Info: TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 D Highest Performance Floating-Point Digital D D D D D D D D D Signal Processor DSP − TMS320C44-60: 33-ns Instruction Cycle Time, 330 MOPS, 60 MFLOPS, 30 MIPS, 336M Bytes/s

EXCCET103

Abstract: INVERTER 20kW SPRU011 C6701 MC68360 MPC860 PCI9050 TMS320C6000 TMS320C6201 TMS320C6701
Contextual Info: TMS320C6701 FLOATING-POINT DIGITAL SIGNAL PROCESSOR SPRS067F − MAY 1998 − REVISED MARCH 2004 D Highest Performance Floating-Point Digital D D D D D Signal Processor DSP TMS320C6701 − 8.3-, 6.7-, 6-ns Instruction Cycle Time − 120-, 150-, 167-MHz Clock Rate

Contextual Info: TMS320C6712, TMS320C6712C FLOATINGĆPOINT DIGITAL SIGNAL PROCESSORS SPRS148D – AUGUST 2000 – REVISED MARCH 2003 D Best Price/Performance Digital Signal D D D D D Processors DSPs : TMS320C67x (TMS320C6712, TMS320C6712C) – Eight 32-Bit Instructions/Cycle

Contextual Info: TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D FLOATINGĆPOINT DIGITAL SIGNAL PROCESSORS SPRS088M − FEBRUARY 1999 − REVISED FEBRUARY 2005 D Excellent-Price/Performance Floating-Point D D D D D Digital Signal Processors DSPs : TMS320C67x (C6711, C6711B, C6711C,