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    MULTI-CHANNEL HDLC CONTROLLER Search Results

    MULTI-CHANNEL HDLC CONTROLLER Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    SSM6J808R Toshiba Electronic Devices & Storage Corporation MOSFET, P-ch, -40 V, -7 A, 0.035 Ohm@10V, TSOP6F, AEC-Q101 Visit Toshiba Electronic Devices & Storage Corporation
    SSM6K819R Toshiba Electronic Devices & Storage Corporation MOSFET, N-ch, 100 V, 10 A, 0.0258 Ohm@10V, TSOP6F, AEC-Q101 Visit Toshiba Electronic Devices & Storage Corporation
    SSM6K809R Toshiba Electronic Devices & Storage Corporation MOSFET, N-ch, 60 V, 6.0 A, 0.036 Ohm@10V, TSOP6F, AEC-Q101 Visit Toshiba Electronic Devices & Storage Corporation
    SSM6K504NU Toshiba Electronic Devices & Storage Corporation MOSFET, N-ch, 30 V, 9.0 A, 0.0195 Ohm@10V, UDFN6B, AEC-Q101 Visit Toshiba Electronic Devices & Storage Corporation
    SSM3K361R Toshiba Electronic Devices & Storage Corporation MOSFET, N-ch, 100 V, 3.5 A, 0.069 Ohm@10V, SOT-23F, AEC-Q101 Visit Toshiba Electronic Devices & Storage Corporation

    MULTI-CHANNEL HDLC CONTROLLER Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    01L-A

    Abstract: multi 9 ihp 1c multi 9 ihp 2c CRC-16 CRC-32
    Text: MCHDLC Device Multi-Channel HDLC Controller TXC-05132 FEATURES DESCRIPTION • Eight serial interfaces The TranSwitch MCHDLC is a Multi-Channel HDLC Controller VLSI device, which is designed to send and receive packets over 256 link channels using eight serial


    Original     		PDF TXC-05132 TXC-05132-MB 01L-A multi 9 ihp 1c multi 9 ihp 2c CRC-16 CRC-32

    JT-Q703

    Abstract: mindspeed pbga 23mm hdlc M28480 Q781
    Text: > Product Overview Multi-Channel HDLC controller with enhanced SS7 support The M28480 is the next generation advanced multi-channel synchronous communications controller MUSYCC that formats and de-formats 512 bi-directional high-level datalink control (HDLC) channels. MUSYCC-512 operates at Layer


    Original     		PDF M28480 MUSYCC-512 M28480-BRF-001-C M28480-11 M28480G-11 JT-Q703 mindspeed pbga 23mm hdlc Q781

    ITR17

    Abstract: ITR24 80X86 AD10 AD11 AD12 AD14 ITR28
    Text: 29C94 MATRA MHS Multi-Channel HDLC Protocol Controller Description The MHS 29C94 is a multi channel data link protocol controller device. It multiplexes/demultiplexes up to 32 full duplex data channels to support implementation of high speed data links based on either HDLC protocol or


    Original     		PDF 29C94 29C94 ITR17 ITR24 80X86 AD10 AD11 AD12 AD14 ITR28

    hdlc

    Abstract: CRC16 STS-48 WA01 WA02 NORTEL OC-12 "watermark" WA03
    Text: Preliminary Data Sheet WA02 A high-density HDLC communications processor Highlights Introduction * Supports up to 1024-channel HDLC processing for four channelized, unchannelized or transparent DS3/E3s The Nortel Networks WA02 is a highdensity, multi-channel HDLC Highlevel Data Link Control


    Original     		PDF 1024-channel hdlc CRC16 STS-48 WA01 WA02 NORTEL OC-12 "watermark" WA03

    VHDL CODE FOR HDLC controller

    Abstract: VHDL CODE FOR HDLC vhdl code for pcm bit stream generator slot machine block diagram vhdl
    Text: Multi-Channel HDLC Controller with PCI Interface Today, there is a variety of HDLC controller chips available from companies like Rockwell Semiconductor, PMC-Sierra and Siemens. Additionally, microprocessors from Motorola and AMD integrate HDLC controllers onchip. These solutions strive to offer flexibility and high


    Original     		PDF 16-bit 1-800-LATTICE VHDL CODE FOR HDLC controller VHDL CODE FOR HDLC vhdl code for pcm bit stream generator slot machine block diagram vhdl

    VHDL CODE FOR HDLC controller

    Abstract: Multi-Channel hdlc Controller vhdl code for pcm bit stream generator VHDL CODE FOR HDLC interrupt controller in vhdl code hdlc C1000 cpldbased slot machine block diagram vhdl
    Text: Multi-Channel HDLC Controller with PCI Interface cellular base-station or Internet Protocol IP on xDSL transport. Introduction High-level Data Link Control (HDLC) is one of the most enduring and fundamental standards in communications. Having its roots in IBM’s x.25 protocol, HDLC is


    Original     		PDF

    VHDL CODE FOR HDLC controller

    Abstract: VHDL CODE FOR HDLC vhdl code CRC 32 vhdl code for sdram controller vhdl code for pcm bit stream generator C1000 PCMT Multi-Channel hdlc Controller motorola C1000 slot machine block diagram vhdl
    Text: Multi-Channel HDLC Controller with PCI Interface cellular base-station or Internet Protocol IP on xDSL transport. Introduction High-level Data Link Control (HDLC) is one of the most enduring and fundamental standards in communications. Having its roots in IBM’s x.25 protocol, HDLC is


    Original     		PDF

    hdlc

    Abstract: LC4256ZE 4000ZE CRC-16 CRC-32 VHDL CODE FOR HDLC controller ispLEVER iso
    Text: HDLC Controller Implemented in ispMACH 4000ZE and CPLD Families July 2009 Reference Design RD1009 Introduction High-Level Data Link Control HDLC is published by the International Standards Organization (ISO). This data link protocol is located at the link layer (layer 2) of the 7-layer OSI reference model. Today, a variety of link layer protocols such as LAPB, LAPD, LLC and SDLC are based on the HDLC protocol with a few modifications. These singlechannel and multi-channel HDLC controller reference designs, targeted for the ispMACH 4000ZE, 4000 and


    Original     		PDF 4000ZE RD1009 4000ZE, 5000VG LC4256ZE-7MN144C, 1-800-LATTICE hdlc LC4256ZE CRC-16 CRC-32 VHDL CODE FOR HDLC controller ispLEVER iso

    Untitled

    Abstract: No abstract text available
    Text: DATA SHEET Communications T3/STS-1/E3 XRT72L52 Two-Channel DS3/E3 Framer IC with HDLC Controller Innovative silicon solutions are a hallmark of Exar's products for the communications markets. Exar offers a full line of multi-channel 1,2,3,4,6 & 8 framers for DS3/E3 network


    Original     		PDF XRT72L52

    Untitled

    Abstract: No abstract text available
    Text: DATA SHEET Communications T3/STS-1/E3 XRT72L50 Single-channel DS3/E3 Framer IC with HDLC Controller Innovative silicon solutions are a hallmark of Exar's products for the communications markets. Exar offers a full line of multi-channel 1,2,3,4,6 & 8 framers for DS3/E3 network


    Original     		PDF XRT72L50

    689-pin

    Abstract: MPC8308 P1010 BSC9132
    Text: PowerQUICC, QorIQ and QorIQ Qonverge Processors Eyebrow Innovation. Connectivity. Freedom. freescale.com PowerQUICC and QorIQ Processors Selector Guide Processor Selector Guide PowerQUICC II Part Number Speed MHz Ethernet E1/T1 E3/T3 UTOPIA Multi-Channel HDLC


    Original     		PDF MPC8247 516-pin MPC8248 MPC8270 480-pin MPC83xx 689-pin MPC8308 P1010 BSC9132

    pef20064

    Abstract: multi-channel router
    Text: Product Brief Infineon MUNICH64 Multi-channel Network Interface Controller for 64 Channels with PCI Main Features The Infineon® MUNICH64 is a highly integrated protocol controller that implements HDLC High-Level Data Link Control , PPP (Point-to-Point Protocol), SS7


    Original     		PDF MUNICH64 MUNICH64 B167-H9319-X-X-7600 pef20064 multi-channel router

    CRC-32

    Abstract: FREEDM-32P672 GPIC672 PM7380 RHDL672 PM4314
    Text: PMC-Sierra,Inc. Preliminary PM7380 FREEDM-32P672 Frame Engine and Data Link Manager FEATURES The FREEDM32P672 chip offers the following features: • Single-chip multi-channel HDLC controller with a 66 MHz, 32-bit Peripheral Component Interconnect PCI 2.1 compliant bus for


    Original     		PDF PM7380 FREEDM-32P672 FREEDM32P672 32-bit PM4314 FREEDM32P672 PM6388 CRC-32 FREEDM-32P672 GPIC672 PM7380 RHDL672 PM4314

    Multi-Channel hdlc Controller

    Abstract: hdlc CRC-32 FREEDM-32P672 GPIC672 PM7380 RHDL672 THDL672 PM7329
    Text: PM7380 FREEDM-32P672 PMC-Sierra,Inc. Frame Engine and Data Link Manager FEATURES The FREEDM-32P672 chip offers the following features: • Single-chip multi-channel HDLC controller with a 66 MHz, 32-bit Peripheral Component Interconnect PCI 2.1 compatible bus for


    Original     		PDF PM7380 FREEDM-32P672 FREEDM-32P672 32-bit PM4354 PM7329 S/UNI-APEX1K800 PM7328 S/UNIATLAS1K800 PMC-1980245 Multi-Channel hdlc Controller hdlc CRC-32 GPIC672 PM7380 RHDL672 THDL672 PM7329

    Untitled

    Abstract: No abstract text available
    Text: PREVIEW H IM mWWmSM SEPTEMBER 1988 DATA SHEET_29C94 MULTI CHANNEL HDLC CONTROLLER _ MAIN FEATURES_ • TARGETTED FOR ISON PRIMARYACCESS 23B+D OR 30B+D HDLC LAYER 2 PROCESSING • SUPPORTS UPTO 31 64 Kb/s FULL DUPLEX


    OCR Scan     		PDF 29C94 29C94

    ITR30

    Abstract: 0804H
    Text: Tem ic 29C94 MATRA MHS Multi-Channel HDLC Protocol Controller Description The MHS 29C94 is a multi channel data link protocol controller device. It multiplexes/demultiplexes up to 32 full duplex data channels to support implementation of high speed data links based on


    OCR Scan     		PDF 29C94 MHS29C94 29C3XX 29C96, 29C94 ITR30 0804H

    CD 40818 BE

    Abstract: capacitor PMR 202 DM preset 103 CD4400 ARM7 ISA RW185 40818 SPC3 st c transistor 40410 CL-CD4400s
    Text: CL-CD4400 'CIRRUSIDG/C Advance Data Book FEATURES • Four full-duplex, multi-protocol serial channels ■ All channels support async-HDLC/PPP, async, HDLC, or programmable sync ■ Sync bit rates up to 8 Mbits/sec. on all channels; up to 52 Mbits/sec. on a single channel in HDLC or


    OCR Scan     		PDF CL-CD4400 inte83 CD 40818 BE capacitor PMR 202 DM preset 103 CD4400 ARM7 ISA RW185 40818 SPC3 st c transistor 40410 CL-CD4400s

    RFC-1331

    Abstract: 105GT-2 80X86 CL-CD2401 CL-CD2431 gt22a iso 3309
    Text: CL-CD2430/CD2431 DataBook i "CIRRUS LOGIC FEATURES • Intelligent 4-Channel Local and WAN Communications Controller Four full-duplex multi-protocol channels, each running up to 128 kbits/second ■ Supports async, async-HDLC high-level data link control , and HDLC/SDLC (synchronous data link


    OCR Scan     		PDF CL-CD2430/CD2431 32-bit 16-bit RFC-1331 RFC-1331 105GT-2 80X86 CL-CD2401 CL-CD2431 gt22a iso 3309

    DM 311 BG 40

    Abstract: DM 311 BG 42 K/DM 311 BG 29 DM 311 BG 30
    Text: Tem ic 29C94 MATRA MHS Multi-Channel HDLC Protocol Controller Description T he MHS 29C94 is a multi channel data link protocol controller device. It multiplexes/demultiplexes up to 32 full duplex data channels to support im plem entation of high speed data links based on


    OCR Scan     		PDF 29C94 29C94 29C3XX 29C96, DM 311 BG 40 DM 311 BG 42 K/DM 311 BG 29 DM 311 BG 30

    Untitled

    Abstract: No abstract text available
    Text: DATA SHEET p iv r PMC-960758 ISSUE 5 1 PMC-Sierra, Inc. PM7364 f r e e d m -32 FRAME ENGINE AND DATA LINK MANAGER FEATURES • Single-chip Peripheral Component Interconnect PCI Bus multi-channel HDLC controller. • Supports up to 128 bi-directional HDLC channels assigned to a maximum of


    OCR Scan     		PDF PMC-960758 PM7364 20X20

    Untitled

    Abstract: No abstract text available
    Text: DATA SHEET p iv r PMC-970930 ISSUE 2 1 PMC-Sierra, Inc. PM7366 f r e e d m -8 FRAME ENGINE AND DATA LINK MANAGER FEATURES • Single-chip Peripheral Component Interconnect PCI Bus multi-channel HDLC controller. • Supports up to 128 bi-directional HDLC channels assigned to a maximum of


    OCR Scan     		PDF PMC-970930 PM7366 20X20

    Untitled

    Abstract: No abstract text available
    Text: C L -C D 4 4 0 0 Advance D a ta Book ' c ir r u s L O G IC FEATURES High-Performance Four-Channel Communications Controller • Four full-duplex, multi-protocol serial channels ■ All channels support async-HDLC/PPP, async, HDLC, or programmable sync ■ Sync bit rates up to 8 Mbits/sec. on all channels;


    OCR Scan     		PDF CL-CD4400

    Untitled

    Abstract: No abstract text available
    Text: CIRRUS LOGIC FEATURES Data Sheet Four-Channel, Multi-Protocol Communications Controller GeneraI • Four full-duplex channels ■ All channels support async, bisync, HDLC/ SDLC, and X.21 programmable sync protocols ■ Bit rates to 64 kbit transmit and receive NRZ,


    OCR Scan     		PDF

    Untitled

    Abstract: No abstract text available
    Text: MCHDLC Device tm ah S w it c h x - D Multi-Channel HDLC Controller TXC-05132 FEATURES DESCRIPTION • Eight serial interfaces - T1/DS1, E1, MVIP, unchannelized two inputs/outputs at up to 8 Mbit/s each - Independent link assignments for receive


    OCR Scan     		PDF TXC-05132