MUX81P Search Results

jk 13001 TRANSISTOR

Abstract: jk 13001 13001 S 6D TRANSISTOR jk 13001 h signo 723 operation manual jk 13001 E bd4 lsi logic 0 281 020 099 SIS transistors 13001 s bd 13001 S 6D TRANSISTOR circuit
Contextual Info: LSI LOGIC LCA500K Prelim inary D esig n M anual June 1995 S304 A0 4 O O n s t M h3? This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an officer of LSI Logic Corporation.

TC200G02 toshiba

Abstract: TC200G70 bt816 cnh 743 YMUX24H toshiba TC200 CNH 532 TC200E240 Transistor AC 51 0865 75 834 BT16ODFS
Contextual Info: ASIC DATA BOOK TC200G/E SERIES MACROCELLS Non-liner Delay Models 1997 ASIC Data Book TC200G/E SERIES MACROCELLS (Non-linear Delay Models) Published in July, 1996 Document ID: 451V1CA (C) Copyright 1996 TOSHIBA Corporation All Rights Reserved The information contained herein is subject to change without notice. The

transistor nd8

Abstract: BT4R ISB28000 bt8c pMOS NAND GATE MUX21L AN720 BUT12 BUT18 BUT24
Contextual Info: ISB28000 SERIES HCMOS EMBEDDED ARRAY PRELIMINARY DATA FEATURES Combines Standard Cell features with Sea Of Gates time to market. 0.7 micron triple layer metal HCMOS process featuring self-aligned twin tub N and P wells, low resistance polysilicide gates and thin metal oxide.

Contextual Info: M T C - 2 2 0 0 0 C M O S 0 .7 n Standard Cell Family Services CMOS Family Features • Technology: CMOS 0 .7 m icron, double or triple la y e r m etal digital or m ix e d a n a lo g /d ig ita l processes, featu rin g self­ aligned tw in tub N an d P w ells, polycide or polysilicon

ALU IC 74181 circuit diagram

Abstract: sulzer s7 ram 74189 74189 ram 512x16Bit 74189 ram 16 ALU IC 74181 ALU IC 74181 FUNCTION TABLE Ic 7485 comparator function table 4-bit even parity using mux 8-1
Contextual Info: LC A 10 0 K C o m p acte d A r r a y Plus Eva lu a tio n D e vic e T ST LOGIC Preliminary Introduction The LCA100K HCMOS Evaluation Array contains a variety of common logic functions that allow a user to evaluate the performance of the LCA100K Com­ pacted Array Plus™ series from LSI Logic Corpora­

CB12000

Abstract: cd 4847 bt8c dc to ac inverter schematic CB22000 ld3p FD11S FD3S BUT12 BUT18
Contextual Info: CB22000 SERIES HCMOS STANDARD CELL GENERAL DESCRIPTION FEATURES 0.7 micron, double layer metal HCMOS4T process featuring self-aligned twin tub N and P wells, low resistance polysilicide gates and thin metal oxide. 2 - input NAND ND2P delay of 0.30 ns (typ)

dm024

Abstract: A992 transistor and its equivalent LB 11917
Contextual Info: LOGIC LEA300K Embedded Array 5 Volt ASIC Products Databook O c to b e r 1994 This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an officer of LSI Logic Corporation.

ct 4a05

Abstract: ZNR2 transistor book MUX21H TBB 469 ic 437 dflop MUX21L AO72 lm 741 using schmitt trigger
Contextual Info: LSI LCA400K G ate Array Series P roduct D atabook Preliminary March 1995 m 5304A04 ODlflSOO ‘ifl? This document is preliminary. As such, it contains data derived from functional simulations and performance estimates. LSI Logic has not verified either the

DM024

Abstract: oti 2168 CM17B transistor bf 175
Contextual Info: 5304804 LSI LOGIC □□mb7A LCA300K G ate Array 5 V olt Series P roducts D atabook Oct ober 1993 f 55b 5304604 0014b7T 4^2 * L L C Preface The LCA300K Gate Array Product Series Databook is written for logic and system designers who wish to use LSI Logic’s 0.6-micron gate

Contextual Info: M T C -1 2 0 0 0 C M O S 1 .2 u Standard Cell Library Services CMOS Family Features • Technology: - 1.2 micron tw in -w ell CMOS process w ith polycide gates, double layer m etal, linear Ihin oxide capacitors and high ohmic resistors - Shrink capability to

74189 ram

Abstract: ram 74189 74189 ttl 74189 74189 ram 16 grid tie inverter schematics 74189 memory 0m02 74280 pin detail grid tie inverters circuit diagrams
Contextual Info: LC A 100K Com pacted .T M A rray P lu s7 Evaluation D evice T ST LOGIC Preliminary Introduction The LCA100K HCMOS Evaluation Array contains a variety of common logic functions that allow a user to evaluate the performance of the LCA100K Com­ pacted Array Plus series from LSI Logic Corpora­