MVIP Search Results

MT90810

Abstract: MT90810AK FGA10
Contextual Info: CMOS MT90810 Flexible MVIP Interface Circuit Preliminary Information  Features ISSUE 2   • MVIP and ST-BUS compliant • MVIP Enhanced Switching with 384x384 channel capacity 256 MVIP channels; 128 local channels October 1994 Ordering Information

Contextual Info: MT90840  Distributed Hyperchannel Switch Preliminary Information Features Output Mux & Drivers PDo7 Applications • • • • • • Bridging ST-BUS/MVIP buses to high speed Time Division Multiplexed backplanes at SONET rates STS-1, STS-3 High speed isochronous backbones for

HIGHWAY 09a 16 PIN DIAGRAM

Abstract: IDT82V2108 JT-G706 TS16 PBS-1R RBS 3101 A121-01 39f020
Contextual Info: T1 / E1 / J1 OCTAL FRAMER IDT82V2108 PRELIMINARY FEATURES • • • • • • • • • • • • • • • • • APPLICATIONS Octal Framer supporting T1, E1 and J1 Formats Provides programmable system interface to support Mitel STbus, AT&T CHI and MVIP bus, supporting data rates of 1.544 /

MT90810AK3

Abstract: MT90810AK MT90810 MT90866AG2 ZL50030GAG2 ZL50031QEG1
Contextual Info: NOTICE February 12, 2010 Obsolescence Notice To: Customer; Obsolescence Notice: Product Number MT90810AK3 Description Last Time Order Date Last Ship Date Pb-free 256 x 128 Channels Flexible MVIP Interface Circuit August 14, 2010 February 12, 2011 The MT90810 device is being phased out. The below table details possible

FGA10

Abstract: LD3C MT8985 MT90810
Contextual Info: MSAN-148 Application Note An Introduction to MVIPTM and Details on Implementation using the MT90810 CONTENTS ISSUE 1 September 1994 1.0 MVIP 1.0 MVIP 1.1 An Overview 1.2 The History 1.3 The Purpose 1.4 The Architecture • MVIP Bus • MVIP Digital Switching

J1069

Abstract: 53K10 ir46 HIGHWAY 09a 16 PIN DIAGRAM
Contextual Info: T1 / E1 / J1 OCTAL FRAMER IDT82V2108 PRELIMINARY FEATURES • • • • • • • • • • • • • • • • • APPLICATIONS Octal Framer supporting T1, E1 and J1 Formats Provides programmable system interface to support Mitel STbus, AT&T CHI and MVIP bus, supporting data rates of 1.544 /

MT90840

Abstract: MT90840AL MT90840AP 001H 101H ha1076 dta 101 22.53
Contextual Info: MT90840 Distributed Hyperchannel Switch Preliminary Information Features Output Mux & Drivers PDo7 Applications • • • • • • Bridging ST-BUS/MVIP buses to high speed Time Division Multiplexed backplanes at SONET rates STS-1, STS-3 High speed isochronous backbones for

TMS 3450

Abstract: 001H 101H MT90840 MT90840AL MT90840AP
Contextual Info: MT90840 Distributed Hyperchannel Switch Preliminary Information Features Output Mux & Drivers PDo7 Applications • • • • • • Bridging ST-BUS/MVIP buses to high speed Time Division Multiplexed backplanes at SONET rates STS-1, STS-3 High speed isochronous backbones for

FGA10

Abstract: MT8985 MT90810 dso0
Contextual Info:  MSAN-148 Application Note An Introduction to MVIPTM and Details on Implementation using the MT90810 CONTENTS ISSUE 1 September 1994 1.0 MVIP 1.0 MVIP 1.1 An Overview 1.2 The History 1.3 The Purpose 1.4 The Architecture • MVIP Bus • MVIP Digital Switching

DM-24

Abstract: DM-30
Contextual Info: NETWORKING TELEBIT CORPORATION MICA* Granite* Card • ■ ■ ■ ■ ■ ■ V.34bis Compatible Platform For Up to 30 Digital Modems Available in 6, 12, 18, 24, and 30 Modem Configurations Integrated MVIP Bus Ensures Vendor Interoperability With Third Party TDM Based T1, E1, and ISDN

DS21352

Abstract: DS2141A DS2151 DS2152 DS21552 DS21Q352 DS21Q552 DS3120 DS3120N 3of121
Contextual Info: PREMILINARY DS3120 28 Channel T1 Framer www.maxim-ic.com FEATURES § § § § § § § § § § § § § § § § § 28 T1 DS1/ISDN–PRI/J1 framing transceivers All 28 framers are fully independent Directly supports loop timing and external timing Supports H.100 / MVIP 8MHz backplanes

MT90840

Abstract: MT90840AL MT90840AP ha1056 AD5A
Contextual Info: MT90840 Distributed Hyperchannel Switch Data Sheet Features • June 2007 Time slot interchange function between eight pairs of ST-BUS/GCI/MVIP streams 512 channels and parallel data port Ordering Information MT90840AL1 MT90840AP1 MT90840APR1 • Programmable data rates on the parallel port

Contextual Info: @ MT90840 M IT E L Distributed Hyperchannel Switch Advance Information H Features ISSUE 1 Time-slot interchange function between 8 pairs of ST-BUS/GCI/MVIP streams 512 channels and a Parallel Data Port (PDP) June 1995 Ordering Information MT90840AK 100PinPQ FP

FGA10

Abstract: MT8985 MT90810 FGA10 SPECIFICATION
Contextual Info: MSAN-148 Application Note An Introduction to MVIPTM and Details on Implementation using the MT90810 CONTENTS ISSUE 1 September 1994 1.0 MVIP 1.0 MVIP 1.1 An Overview 1.2 The History 1.3 The Purpose 1.4 The Architecture • MVIP Bus • MVIP Digital Switching

Contextual Info: CMOS MT90810 Flexible MVIP Interface Circuit Features • • • • • • • • • ISSUE 3 MVIP and Ordering Information ST-BUS compliant MT90810AK 100 Pin PQFP 0 °C to +70 °C MVIP Enhanced Switching with 384x384 channel capacity 256 MVIP channels; 128

MT8910

Abstract: MT8972B MT90840 MT90840AK MT90840AP MUX2-b 8029 multiplexer
Contextual Info: MT90840  Distributed Hyperchannel Switch Advance Information Features ISSUE 1 June 1995 • Time-slot interchange function between 8 pairs of ST-BUS/GCI/MVIP streams 512 channels and a Parallel Data Port (PDP) • Supports star, point to point connections and

diode DS1

Abstract: ECTF
Contextual Info: KEY FEATURES of the T3BwB TXC-06826 E Interfaces G ES CONNECTIVI TY 01 00 10 10 1 1 1 1 1 DS3 or 28 DS1s 1 • Line: N IN R FO L OBA GL 1 • Terminal: Unframed DS1, transmission DS1, and either H.100/H.110 or MVIP bus support 1 1 TXC-06826 T3BwP 10 10 00

Contextual Info: MT90840  Distributed Hyperchannel Switch Preliminary Information Features Output Mux & Drivers PDo7 Applications • • • • • • Bridging ST-BUS/MVIP buses to high speed Time Division Multiplexed backplanes at SONET rates STS-1, STS-3 High speed isochronous backbones for

Contextual Info: MCHDLC Device tm ah S w it c h x - D Multi-Channel HDLC Controller TXC-05132 FEATURES DESCRIPTION • Eight serial interfaces - T1/DS1, E1, MVIP, unchannelized two inputs/outputs at up to 8 Mbit/s each - Independent link assignments for receive

Contextual Info: MVIP, MVIL, and MVIV Series ¾ MIL-STD-883 Level B Screening Available ¾ Available to -55°C to + 125°C Operating ¾ RoHS Compliant ¾ Less than 1 pSec Jitter ELECTRICAL SPECIFICATIONS: LVDS Frequency Range Frequency Stability* Operating Temp.Range Storage Temp. Range

FGA10

Abstract: ZXd 27 LD01 LD02 MT9081 MT90810 FGB11 FC4L
Contextual Info: CM O S MITEL MT90810 Flexible MVIP Interface Circuit Prelim inary Inform ation Features _ ISSUE 3_March 1997 Ordering Information • • • MVIP and ST-BUS™ compliant MVIP Enhanced Switching with 384x384 channel capacity 256 MVIP channels; 128

TMS 3450

Abstract: FGA10 MT90810 MT90810AK
Contextual Info: CMOS MT90810 Flexible MVIP Interface Circuit Features • • • • • • • • • ISSUE 3 MVIP and Ordering Information ST-BUS compliant MT90810AK 100 Pin PQFP 0 °C to +70 °C MVIP Enhanced Switching with 384x384 channel capacity 256 MVIP channels; 128

psd100

Abstract: 001H 101H MT90840 MT90840AL MT90840AP
Contextual Info: MT90840 Distributed Hyperchannel Switch Data Sheet Features Output Mux & Drivers PDo7 Applications • • • • • • Bridging ST-BUS/MVIP buses to high speed Time Division Multiplexed backplanes at SONET rates STS-1, STS-3 High speed isochronous backbones for

Contextual Info: CMOS MITEL MT90810 Flexible MVIP Interface Circuit Preliminary Information Features ISSUE 2 • MVIP and ST-BUS™ compliant • MVIP Enhanced Switching with 384x384 channel capacity 256 MVIP channels; 128 local channels O ctober 1994 O rdering Inform ation