NAND GATES IN 2 UNITS Search Results

DM54L00J

Contextual Info: DM54L00 DM54L00 Quad 2-Input NAND Gates Literature Number: SNOS264A DM54L00 Quad 2-Input NAND Gates General Description This device contains four independent gates each of which performs the logic NAND function Connection Diagram Function Table Dual-In-Line Package

ACT132

Contextual Info: MC74AC132, MC74ACT132 Quad 2-Input NAND Schmitt Trigger The MC74AC/74ACT132 contains four 2−input NAND gates which are capable of transforming slowly changing input signals into sharply defined, jitter−free output signals. In addition, they have greater noise margin than conventional NAND gates.

act132

Abstract: AC-132 MC74AC132 MC74AC132D MC74AC132DR2 MC74AC132N MC74ACT132 MC74ACT132D MC74ACT132DR2 MC74ACT132N
Contextual Info: MC74AC132, MC74ACT132 Quad 2−Input NAND Schmitt Trigger The MC74AC/74ACT132 contains four 2−input NAND gates which are capable of transforming slowly changing input signals into sharply defined, jitter−free output signals. In addition, they have greater noise margin than conventional NAND gates.

74ac132

Abstract: AC132G ACT132G 74AC ACT132 MC74AC132 MC74AC132N MC74ACT132 SOEIAJ-14 MC74AC132NG
Contextual Info: MC74AC132, MC74ACT132 Quad 2−Input NAND Schmitt Trigger The MC74AC/74ACT132 contains four 2−input NAND gates which are capable of transforming slowly changing input signals into sharply defined, jitter−free output signals. In addition, they have greater noise margin than conventional NAND gates.

AC132G

Abstract: ACT132G 74ac132 74act132 AC-132G act132 on 74AC ACT132 MC74AC132 MC74AC132N
Contextual Info: MC74AC132, MC74ACT132 Quad 2−Input NAND Schmitt Trigger The MC74AC/74ACT132 contains four 2−input NAND gates which are capable of transforming slowly changing input signals into sharply defined, jitter−free output signals. In addition, they have greater noise margin than conventional NAND gates.

AC132G

Contextual Info: MC74AC132, MC74ACT132 Quad 2−Input NAND Schmitt Trigger The MC74AC/74ACT132 contains four 2−input NAND gates which are capable of transforming slowly changing input signals into sharply defined, jitter−free output signals. In addition, they have greater noise margin than conventional NAND gates.

74ac132

Abstract: 74ACT132 ACT132 MC74AC132 MC74AC132D MC74AC132DR2 MC74AC132N MC74ACT132 MC74ACT132D MC74ACT132DR2
Contextual Info: MC74AC132, MC74ACT132 Quad 2-Input NAND Schmitt Trigger The MC74AC/74ACT132 contains four 2–input NAND gates which are capable of transforming slowly changing input signals into sharply defined, jitter–free output signals. In addition, they have greater noise margin than conventional NAND gates.

AC132

Abstract: 74ac132
Contextual Info: MC74AC132, MC74ACT132 Quad 2-Input NAND Schmitt Trigger The MC74AC/74ACT132 contains four 2–input NAND gates which are capable of transforming slowly changing input signals into sharply defined, jitter–free output signals. In addition, they have greater noise margin than conventional NAND gates.

Contextual Info: GD54/74HC00, GD54/74HCT00 QUAD 2-INPUT NAND GATES General Description These devices are identical in pinout to the 54/74LS00. They contain four independent 2-input NAND gates. These devices are characterized for operation over wide temperature ranges to meet in­

TTL 74HC00

Abstract: 74LS00 TTL TTL 74ls00 74LS00 gate diagram 74ls00 74LS00 function table pin configuration logic symbol 74LS00 logic symbol 74LS00 74HC00 5V 74HC00
Contextual Info: GD54/74HC00, GD54/74HCT00 QUAD 2-INPUT NAND GATES General Description These devices are identical in pinout to the 54/74LS00. They contain four independent 2-input NAND gates. These devices are characterized for operation over wide temperature ranges to meet in­

74LS00 pinout

Abstract: GD74HC00 pin configuration logic symbol 74LS00 logic symbol 74LS00 74HC00 5V 74HC00 74hc00 and gates TTL 74HC00 74HC GD54HC00
Contextual Info: GDS4/74HC00, GD54/74HCT00 QUAD 2-INPUT NAND GATES General Description These devices are identical in pinout to the 54/74LS 00. They contain four independent 2-input NAND gates. These devices are characterized for operation over wide temperature ranges to meet in­

74HCoo

Abstract: TTL 74HC00 74LS00 pinout pin diagram of 74ls00 74HC00 GD74HC00 logic symbol 74LS00 74hc00 and gates pin configuration logic symbol 74LS00 74LS00 gate diagram
Contextual Info: GD54/74HC00, GD54/74HCT00 QUAD 2-INPUT NAND GATES General Description These devices are identical in pinout to the 54/74LS 00. They contain four independent 2-input NAND gates. These devices are characterized for operation over wide temperature ranges to meet in­

DM74S00N

Abstract: DM54S00 DM54S00J DM54S00W DM74S00 DM74S00M J14A M14A N14A W14B
Contextual Info: DM54S00 DM74S00 Quad 2-Input NAND Gates General Description This device contains four independent gates each of which performs the logic NAND function Connection Diagram Dual-In-Line Package TL F 6489 – 1 Order Number DM54S00J DM54S00W DM74S00M or DM74S00N

Contextual Info: o National ÆSt Semiconductor DM54L00 Quad 2-lnput NAND Gates General Description This device contains four independent gates each of which performs the logic NAND function. Connection Diagram Function Table Dual-In-Line Package Y = AB Output Inputs H “

DM54L00J

Contextual Info: June 1989 Semiconductor DM54L00 Quad 2-Input NAND Gates General Description This device contains four independent gates each of which performs the logic NAND function. Connection Diagram Function Table Dual-In-Line Package Y = AB Inputs Output A B Y L L H

DM74S00N

Abstract: DM74S00 DM54S00J DM54S00W DM74S00M J14A M14A N14A W14B
Contextual Info: DM74S00 Quad 2-Input NAND Gates General Description This device contains four independent gates each of which performs the logic NAND function. Connection Diagram Dual-In-Line Package DS006489-1 Order Number DM54S00J, DM54S00W, DM74S00M or DM74S00N See Package Number J14A, M14A, N14A or W14B

DM54S20J

Abstract: DM54S20W DM74S20N J14A N14A W14B DM74S20
Contextual Info: , March 1989 DM54S20/DM74S20 Dual 4-Input NAND Gates General Description This device contains two independent gates each of which performs the logic NAND function. Connection Diagram Dual-In-Line Package 02 M çc C2 13 NC 12 I - B2 111 A2 10 9 — 2 1 Al 13

GD74HC20

Abstract: GD74HCT20
Contextual Info: GD54/74HC20, GD54/74HCT20 DUAL 4-INPUT NAND GATES General Description These devices Pin Configuration are identical in pinout to the 5 4 /7 4 L S 2 0 . They contain two independent 4 -input NAND gates. These devices are characteriz­ ed for operation over wide temperature ranges to

Contextual Info: June 1989 DM54S00/DM74S00 Quad 2-Input NAND Gates General Description This device contains four independent gates each of which performs the logic NAND function. Connection Diagram Dual-In-Line Package V cc B4 A4 Y4 B3 A3 Y3 AI Bl Y1 A2 B2 Y2 GMD TL/F/6489-1

DM54L10

Abstract: DM54L10J DM54L10W J14A W14B
Contextual Info: , June 1989 DM54L10 Triple 3-Input NAND Gates General Description This device contains three independent gates each of which performs the logic NAND function. Connection Diagram Dual-In-Line Package Vcc Cl |,4 Y1 13 C3 B3 11 12 A3 10 Y3 9 8 =5 ED 1 A1 2 D -

GD74HCT03

Abstract: GD74HC03
Contextual Info: GD54/74HC03, GD54/74HCT03 QUAD 2-INPUT NAND GATES WITH OPEN-DRAIN OUTPUTS General Description Pin Configuration These devices are identical in pinout to the 54/74LS03. They contain four independent 2-Input NAND gates. The open-drain outputs require pullup resistors to perform correctly. With suitable pullup resistors, these devices can be used in activelow wired-OR or active-high wired-AND applica­

f6654

Abstract: DM54L00J C1995 DM54L00 DM54L00W J14A W14B f 6654
Contextual Info: DM54L00 Quad 2-Input NAND Gates General Description This device contains four independent gates each of which performs the logic NAND function Connection Diagram Function Table Dual-In-Line Package Y e AB Inputs Output A B Y L L H H L H L H H H H L H e High Logic Level

Contextual Info: R C H II- D S E M IC O N D U C T O R tm MM74HC00 Quad 2-Input NAND Gate General Description Features These NAND gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard CMOS in­

DM7413N

Contextual Info: co 5 p^. K&M National s Q co 5 in 2 o Sim Semiconductor DM5413/DM7413 Dual 4-Input NAND Gates with Schmitt Trigger Inputs General Description Absolute Maximum Ratings Note d This device con tains tw o independent gates each of w hich perform s the logic NAND fun ction. Each input