NXP 74LVC1G Search Results
NXP 74LVC1G Result Highlights (5)
Part | ECAD Model | Manufacturer | Description | Download | Buy |
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74LVC1G125DCKRE4 |
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Single Bus Buffer Gate With 3-State Outputs 5-SC70 -40 to 125 |
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74LVC1G126DBVRE4 |
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Single Bus Buffer Gate With 3-State Outputs 5-SOT-23 -40 to 125 |
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74LVC1G132DBVRG4 |
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Single 2-Input NAND Gate with Schmitt-Trigger Input 5-SOT-23 -40 to 125 |
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74LVC1GU04DBVRE4 |
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Single Inverter Gate 5-SOT-23 -40 to 125 |
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74LVC1G123DCURE4 |
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Single Retriggerable Monostable Multivibrator with Schmitt-Trigger Inputs 8-VSSOP -40 to 125 |
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NXP 74LVC1G Datasheets Context Search
Catalog Datasheet | Type | Document Tags | |
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JESD22-C101EContextual Info: Demonstrate seven different logic functions NXP demo board for the configurable logic device 74AUP1T97 NXP demo board for the configurable logic device 74AUP1T97 Key features and benefits } Wide supply voltage range: 2.3 to 3.6 V } High noise immunity } Excellent ESD protection |
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74AUP1T97 JESD22-A114F JESD22-A115-A JESD22-C101E | |
LPC2148 i2c
Abstract: BGB210S lpc2148 interfacing 2.8" TFT LCD DISPLAY BGB210 embedded c code to interface lpc2148 with sensor BGW200 TDA8932T tda8920bj NXP PN531 TDA8947J equivalent
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OT363 SC-88) LPC2148 i2c BGB210S lpc2148 interfacing 2.8" TFT LCD DISPLAY BGB210 embedded c code to interface lpc2148 with sensor BGW200 TDA8932T tda8920bj NXP PN531 TDA8947J equivalent | |
NXP AVC8T245Contextual Info: NXP demo board for configurable logic device 74AXP1G57 Demonstrate seven different logic functions This compact board makes it easy to evaluate all seven functions of the 74AXP1G57 Key features and benefits `` Wide supply voltage range: 0.7 to 2.75 V `` High noise immunity |
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74AXP1G57 JS-001 JESD22-C101E 74AXP1G57 NXP AVC8T245 | |
3Gxxx
Abstract: 1G14 1G157 MICROPAK XX 1G04 sot363 xg 1G57 SOT891 1G02 TC7S
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web cam
Abstract: CBT3306 NX5DV330 AEC-Q100 JESD22-A114E NX3L1T3157GM NX3L1T66 NX3V1G384GM NX3V1G384GW mobile phone cam circuit diagram
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NX5DV330 web cam CBT3306 AEC-Q100 JESD22-A114E NX3L1T3157GM NX3L1T66 NX3V1G384GM NX3V1G384GW mobile phone cam circuit diagram | |
NXP PN65n
Abstract: NXP PN544 PN544 hardware design guide NXP PN544 Antenna Design Guide nfc PN65N PN544 PN544 NFC controller nxp pn544 antenna design PN544 NFC PN544 nxp
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SN74HC logic family
Abstract: SOT505-2 SOT363-6 SOT891 HEF4000 series SOT753 footprint sn74abt fairchild AHC 14 cd4xxx SOT353-1 footprint
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HEF4000 so891 SN74HC logic family SOT505-2 SOT363-6 SOT891 HEF4000 series SOT753 footprint sn74abt fairchild AHC 14 cd4xxx SOT353-1 footprint | |
IP4223CZ6
Abstract: uba2074 uba2072 UBA2071 uba*2074 ip4223 UBA2072, UBA2074 UBA2071A uhf varicap UBA2074A
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M74HCxxxTTR
Abstract: 74ABT FAIRCHILD HEF4000B MM74HC nxp Cross-reference HEF4000 LVT32 SN74HC 74HC HC PORTFOLIO
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anOT891 M74HCxxxTTR 74ABT FAIRCHILD HEF4000B MM74HC nxp Cross-reference HEF4000 LVT32 SN74HC 74HC HC PORTFOLIO | |
PCA9698DGG
Abstract: PCA9698 OM6275 PCA9530 IO42 74LVC1G38 UM10267
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UM10267 PCA9698 OM6281 PCA9698, OM6281 40-bit PCA9698DGG OM6275 PCA9530 IO42 74LVC1G38 UM10267 | |
7SDMM-B0-2211-A
Abstract: 980020-48-P2 mt29f2g08aadwp connector 7sdmm-b0-2211 MT29F8G08AAAWP MT29F8G08A MT29F2G08AAD BSS138 NXP 7SDMM 7SDMM-B0-2211
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SCH-VAL314x-01 LPC314x LPC3143 GPIO19; GPIO20 7SDMM-B0-2211-A 980020-48-P2 mt29f2g08aadwp connector 7sdmm-b0-2211 MT29F8G08AAAWP MT29F8G08A MT29F2G08AAD BSS138 NXP 7SDMM 7SDMM-B0-2211 | |
980020-48-P2
Abstract: 7SDMM-B0-2211-A MT29F8G08AAAWP mt29f2g08aadwp MT29F8G08A 7SDMM-B0-2211 MT29F2G08AAD 7SDMM MT29F4G08ABCWC MT29F4G08ABCWC-et
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SCH-VAL313x-01 LPC313x LPC314x GPIO19; GPIO20 980020-48-P2 7SDMM-B0-2211-A MT29F8G08AAAWP mt29f2g08aadwp MT29F8G08A 7SDMM-B0-2211 MT29F2G08AAD 7SDMM MT29F4G08ABCWC MT29F4G08ABCWC-et | |
hef4051
Abstract: 74AUP2G34 74LVT1403 74ABT543A 74LV74 74AVCH1T45 74HC590 CBTD3306 NCX2200 74HC40103
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Contextual Info: 74LVC1G19 1-of-2 decoder/demultiplexer Rev. 7 — 10 September 2014 Product data sheet 1. General description The 74LVC1G19 is a 1-of-2 decoder/demultiplexer with a common output enable. This device buffers the data on input A and passes it to the outputs 1Y true and 2Y |
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74LVC1G19 74LVC1G19 | |
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Contextual Info: 74LVC1G157 Single 2-input multiplexer Rev. 5 — 6 December 2011 Product data sheet 1. General description The 74LVC1G157 is a single 2-input multiplexer which select data from two data inputs I0 and I1 under control of a common data select input (S). The state of the common data |
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74LVC1G157 74LVC1G157 | |
application note sot353-1 nxpContextual Info: 74LVC1G86 2-input EXCLUSIVE-OR gate Rev. 9 — 5 March 2012 Product data sheet 1. General description The 74LVC1G86 provides the 2-input EXCLUSIVE-OR function. Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment. |
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74LVC1G86 74LVC1G86 JESD8B/JESD36 application note sot353-1 nxp | |
Contextual Info: 74LVC1G06 Inverter with open-drain output Rev. 9 — 7 December 2011 Product data sheet 1. General description The 74LVC1G06 provides the inverting buffer. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment. |
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74LVC1G06 74LVC1G06 | |
Contextual Info: 74LVC1GU04 Inverter Rev. 11 — 2 July 2012 Product data sheet 1. General description The 74LVC1GU04 provides the inverting single state unbuffered function. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. |
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74LVC1GU04 74LVC1GU04 JESD22-A114F JESD22-A115-A | |
Contextual Info: 74LVC1G86 2-input EXCLUSIVE-OR gate Rev. 10 — 2 July 2012 Product data sheet 1. General description The 74LVC1G86 provides the 2-input EXCLUSIVE-OR function. Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment. |
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74LVC1G86 74LVC1G86 JESD8B/JESD36 | |
Contextual Info: 74LVC1G04 Single inverter Rev. 12 — 6 August 2012 Product data sheet 1. General description The 74LVC1G04 provides one inverting buffer. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment. |
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74LVC1G04 74LVC1G04 | |
Contextual Info: 74LVC1G32 Single 2-input OR gate Rev. 10 — 4 September 2012 Product data sheet 1. General description The 74LVC1G32 provides one 2-input OR function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications. |
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74LVC1G32 74LVC1G32 | |
74LVC1G34Contextual Info: 74LVC1G34 Single buffer Rev. 5 — 2 July 2012 Product data sheet 1. General description The 74LVC1G34 provides a low-power, low-voltage single buffer. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. |
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74LVC1G34 74LVC1G34 | |
74lvc1g97Contextual Info: 74LVC1G97 Low-power configurable multiple function gate Rev. 3 — 7 December 2011 Product data sheet 1. General description The 74LVC1G97 is a configurable multiple function gate with Schmitt-trigger inputs. The device can be configured as any of the following logic functions MUX, AND, OR, NAND, |
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74LVC1G97 74LVC1G97 | |
Contextual Info: 74LVC1G38 2-input NAND gate; open drain Rev. 6 — 2 July 2012 Product data sheet 1. General description The 74LVC1G38 provides a 2-input NAND function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device as translator in a mixed 3.3 V and 5 V environment. |
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74LVC1G38 74LVC1G38 |