NXP MARKING A14 Search Results

A22 SMD MARKING CODE

Abstract: SMD MARKING CODE 1D6 SMD MARKING CODE 1D7 SMD MARKING CODE 2d1 A30 MARKING CODE 2D4 SMD marking a26 smd marking A26 smd marking code b6 SMD marking code B10
Contextual Info: 74LVC16374A; 74LVCH16374A 16-bit edge-triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state Rev. 06 — 12 February 2009 Product data sheet 1. General description The 74LVC16374A and 74LVCH16374A are 16-bit edge-triggered flip-flops featuring

SMD marking code B10

Abstract: smd marking a26
Contextual Info: 74ALVC164245 16-bit dual supply translating transceiver; 3-state Rev. 04 — 11 November 2008 Product data sheet 1. General description The 74ALVC164245 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

MARKING AF SOT353

Abstract: Q-100 NXP MARKING A14
Contextual Info: 74AHC1G14-Q100; 74AHCT1G14-Q100 Inverting Schmitt trigger Rev. 1 — 13 July 2012 Product data sheet 1. General description 74AHC1G14-Q100 and 74AHCT1G14-Q100 are high-speed Si-gate CMOS devices. They provide an inverting buffer function with Schmitt-trigger action. These devices can

Contextual Info: 74AHC1G14-Q100; 74AHCT1G14-Q100 Inverting Schmitt trigger Rev. 1 — 13 July 2012 Product data sheet 1. General description 74AHC1G14-Q100 and 74AHCT1G14-Q100 are high-speed Si-gate CMOS devices. They provide an inverting buffer function with Schmitt-trigger action. These devices can

NXP MARKING A14

Contextual Info: 74AHC3G14; 74AHCT3G14 Inverting Schmitt trigger Rev. 5 — 23 September 2010 Product data sheet 1. General description 74AHC3G14 and 74AHCT3G14 are high-speed Si-gate CMOS devices. They provide an inverting buffer function with Schmitt trigger action. These devices are capable of

74AHC3G14

Abstract: 74AHC3G14DC 74AHC3G14DP 74AHC3G14GD 74AHCT3G14 74AHCT3G14DC 74AHCT3G14DP JESD22-A114E AHC* marking
Contextual Info: 74AHC3G14; 74AHCT3G14 Inverting Schmitt trigger Rev. 04 — 5 May 2009 Product data sheet 1. General description 74AHC3G14 and 74AHCT3G14 are high-speed Si-gate CMOS devices. They provide an inverting buffer function with Schmitt trigger action. These devices are capable of

Contextual Info: 74AHC3G14-Q100; 74AHCT3G14-Q100 Triple inverting Schmitt trigger Rev. 3 — 16 September 2013 Product data sheet 1. General description 74AHC3G14-Q100 and 74AHCT3G14-Q100 are high-speed Si-gate CMOS devices. They provide three inverting buffers with Schmitt trigger action. These devices are

74AHC3G14

Abstract: 74AHC3G14DC 74AHC3G14DP 74AHCT3G14 74AHCT3G14DC 74AHCT3G14DP
Contextual Info: 74AHC3G14; 74AHCT3G14 Triple inverting Schmitt trigger Rev. 6 — 18 November 2010 Product data sheet 1. General description 74AHC3G14 and 74AHCT3G14 are high-speed Si-gate CMOS devices. They provide three inverting buffers with Schmitt trigger action. These devices are capable of

Contextual Info: 74AHC3G14-Q100; 74AHCT3G14-Q100 Triple inverting Schmitt trigger Rev. 1 — 1 October 2012 Product data sheet 1. General description 74AHC3G14-Q100 and 74AHCT3G14-Q100 are high-speed Si-gate CMOS devices. They provide three inverting buffers with Schmitt trigger action. These devices are

Contextual Info: 74AHC3G14-Q100; 74AHCT3G14-Q100 Triple inverting Schmitt trigger Rev. 2 — 28 January 2013 Product data sheet 1. General description 74AHC3G14-Q100 and 74AHCT3G14-Q100 are high-speed Si-gate CMOS devices. They provide three inverting buffers with Schmitt trigger action. These devices are

Contextual Info: 74AHC3G14; 74AHCT3G14 Triple inverting Schmitt trigger Rev. 7 — 8 November 2011 Product data sheet 1. General description 74AHC3G14 and 74AHCT3G14 are high-speed Si-gate CMOS devices. They provide three inverting buffers with Schmitt trigger action. These devices are capable of

Contextual Info: 74AHC3G14; 74AHCT3G14 Triple inverting Schmitt trigger Rev. 7 — 8 November 2011 Product data sheet 1. General description 74AHC3G14 and 74AHCT3G14 are high-speed Si-gate CMOS devices. They provide three inverting buffers with Schmitt trigger action. These devices are capable of

Contextual Info: 74AHC3G14; 74AHCT3G14 Triple inverting Schmitt trigger Rev. 8 — 13 May 2013 Product data sheet 1. General description 74AHC3G14 and 74AHCT3G14 are high-speed Si-gate CMOS devices. They provide three inverting buffers with Schmitt trigger action. These devices are capable of

74AHC1G14

Abstract: 74AHC1G14GV 74AHC1G14GW 74AHCT1G14 74AHCT1G14GV 74AHCT1G14GW JESD22-A114E marking af sot353
Contextual Info: 74AHC1G14; 74AHCT1G14 Inverting Schmitt trigger Rev. 05 — 29 June 2007 Product data sheet 1. General description 74AHC1G14 and 74AHCT1G14 are high-speed Si-gate CMOS devices. They provide an inverting buffer function with Schmitt trigger action. These devices are capable of

AHCT1G14

Abstract: 74AHC1G14GW 74AHC1G14 74AHC1G14GV 74AHCT1G14 74AHCT1G14GV 74AHCT1G14GW JESD22-A114E
Contextual Info: 74AHC1G14; 74AHCT1G14 Inverting Schmitt trigger Rev. 06 — 18 May 2009 Product data sheet 1. General description 74AHC1G14 and 74AHCT1G14 are high-speed Si-gate CMOS devices. They provide an inverting buffer function with Schmitt trigger action. These devices are capable of

74AHC3G14

Abstract: 74AHC3G14DC 74AHC3G14DP 74AHC3G14GD 74AHCT3G14 74AHCT3G14DC 74AHCT3G14DP JESD22-A114E
Contextual Info: 74AHC3G14; 74AHCT3G14 Inverting Schmitt trigger Rev. 03 — 17 June 2008 Product data sheet 1. General description 74AHC3G14 and 74AHCT3G14 are high-speed Si-gate CMOS devices. They provide an inverting buffer function with Schmitt trigger action. These devices are capable of

LPC3240FET296,551

Abstract: NXP dual interface LPC3250FET296,551 SOT1048-1 sic marking e6
Contextual Info: LPC3220/30/40/50 16/32-bit ARM microcontrollers; hardware floating-point coprocessor, USB On-The-Go, and EMC memory interface Rev. 01 — 6 February 2009 Preliminary data sheet 1. General description The LPC3220/30/40/50 embedded microcontrollers were designed for low power, high

PHY Interface for the PCI Express

Abstract: PX1041A MO-205 sot631 PX1041A-EL1
Contextual Info: PX1041A PCI Express stand-alone X4 PHY Rev. 01 — 21 June 2007 Objective data sheet 1. General description The PX1041A is a high-performance, low-power, four-lane PCI Express electrical PHYsical layer PHY that handles the low level PCI Express protocol and signaling. The

lcd 080530

Abstract: CE-ATA version 1.1 eMMC intel LPC3131 ARM926EJ eMMC 4.4 LPC3130FET180 PS3 wifi ARM926EJ-S LPC3130
Contextual Info: LPC3130/3131 Low-cost, low-power ARM926EJ-S MCUs with high-speed USB 2.0 OTG, SD/MMC, and NAND flash controller Rev. 1 — 9 February 2009 Preliminary data sheet 1. General description The NXP LPC3130/3131 combine an 180 MHz ARM926EJ-S CPU core, high-speed USB

iNAND eMMC 4 41

Abstract: sdhc timing intel emmc NXP Marking H2 muart ARMv5TE ARM926EJ
Contextual Info: LPC3141/3143 Low-cost, low-power ARM926EJ microcontrollers with USB High-speed OTG, SD/MMC, and NAND flash controller Rev. 1 — 4 June 2012 Product data sheet 1. General description The NXP LPC3141/3143 combine a 270 MHz ARM926EJ-S CPU core, High-speed USB

intel date code marking NAND Flash

Abstract: ARMv5TE instruction set MLC nand 2012 153 ball eMMC memory flash controller usb state machine for ahb to apb bridge iNAND eMMC 4 41 emmc spi bridge emmc bga 162 LPC3130FET180
Contextual Info: LPC3130/3131 Low-cost, low-power ARM926EJ-S MCUs with high-speed USB 2.0 OTG, SD/MMC, and NAND flash controller Rev. 2 — 29 May 2012 Product data sheet 1. General description The NXP LPC3130/3131 combine an 180 MHz ARM926EJ-S CPU core, high-speed USB 2.0 On-The-Go OTG , up to 192 KB SRAM, NAND flash controller, flexible external bus

Contextual Info: D D R R R R R D D D FT FT FT FT FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D Low-cost, low-power ARM926EJ microcontrollers with USB High-speed OTG, SD/MMC, and NAND flash controller R R R D D D F FT FT A A Preliminary data sheet A

Contextual Info: SDIO101A SD/SDIO/MMC/CE-ATA host controller Rev. 1 — 13 June 2013 Product data sheet 1. General description The SDIO101A is a SD/SDIO/MMC/CE-ATA host controller with a standard 16-bit asynchronous memory interface. The device conforms to the SD Host Standard

Contextual Info: LPC3152/3154 ARM926EJ microcontrollers with USB High-speed OTG, SD/MMC, NAND flash controller, and audio codec Rev. 1 — 31 May 2012 Product data sheet 1. General description The NXP LPC3152/3154 combine an 180 MHz ARM926EJ-S CPU core, High-speed USB 2.0 OTG, 192 kB SRAM, NAND flash controller, flexible external bus interface, an