O109 MA Search Results

Contextual Info: CY37256V UltraLogic 3.3V 256-Macrocell ISR™ CPLD — tPD = 12 ns Features — tS = 7.0 ns • 256 macrocells in sixteen logic blocks • 3.3V In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming • • • • • • • •

37256p

Abstract: CY37256-125 IEEE 1149.1 JTAG CY37256 CY37256P160-125UMB
Contextual Info: CY37256 UltraLogic 256-Macrocell ISR™ CPLD Features • • • • • • • • • • 256 macrocells in sixteen logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

U208

Contextual Info: PRELIMINARY CY37512V UltraLogic 3.3V 512-Macrocell ISR™ CPLD Features For a more detailed description of the architecture and features of the CY37512V see the Ultra37000 Family data sheet. • 512 macrocells in 32 logic blocks • 3.3V In-System Reprogrammable™ ISR™

tlp 453

Contextual Info: fax id: 6151 PRELIMINARY Ultra37192V UltraLogic 3.3V 192-Macrocell ISR™ CPLD — tPD = 10 ns Features — tS = 5.5 ns • 192 macrocells in twelve logic blocks • IEEE standard 3.3V operation — 3.3V ISR • • • • • • • • • — 5V tolerant

CY37256

Abstract: CY37256V O116
Contextual Info: Back PRELIMINARY CY37256V UltraLogic 3.3V 256-Macrocell ISR™ CPLD — tPD = 12 ns Features — tS = 7 ns • 256 macrocells in sixteen logic blocks • 3.3V In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming • • • • •

CY37256

Abstract: CY37256V
Contextual Info: PRELIMINARY CY37256V UltraLogic 3.3V 256-Macrocell ISR™ CPLD — tPD = 12 ns Features — tS = 7 ns • 256 macrocells in sixteen logic blocks • 3.3V In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming • • • • • •

160LEAD

Contextual Info: fax id: 6140 CY7C375i UltraLogic 128-Macrocell Flash CPLD • Available in 160-pin TQFP, CQFP, and PGA packages Features Functional Description • • • • 128 macrocells in eight logic blocks 128 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogrammable ISR™ Flash technology

CY37512

Abstract: CY37512V
Contextual Info: Back PRELIMINARY CY37512V UltraLogic 3.3V 512-Macrocell ISR™ CPLD — tPD = 15 ns Features • 512 macrocells in 32 logic blocks • 3.3V In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

ULTRA37000

Contextual Info: USE ULTRA37000 FOR ALL NEW DESIGNS CY7C375i UltraLogic™ 128-Macrocell Flash CPLD Features • 3.3V or 5.0V I/O operation • Available in 160-pin TQFP, CQFP, and PGA packages • 128 macrocells in eight logic blocks • 128 I/O pins Functional Description

CERAMIC QUAD FLATPACK CQFP 14 pin

Abstract: CERAMIC QUAD FLATPACK CQFP CERAMIC PIN GRID ARRAY CPGA
Contextual Info: fax id: 6140 CY7C375i UltraLogic 128-Macrocell Flash CPLD Features • Available in 160-pin TQFP, CQFP, and PGA packages Functional Description • • • • 128 macrocells in eight logic blocks 128 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogrammable ISR™ Flash technology

Contextual Info: fax id: 6140 CY7C375i UltraLogic 128-Macrocell Flash CPLD Features Functional Description • • • • 128 macrocells in eight logic blocks 128 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogrammable ISR™ Flash technology — JTAG Interface

ULTRA37000

Abstract: 160-Lead
Contextual Info: USE ULTRA37000 FOR ALL NEW DESIGNS CY7C375i UltraLogic™ 128-Macrocell Flash CPLD Features • 3.3V or 5.0V I/O operation • Available in 160-pin TQFP, CQFP, and PGA packages • 128 macrocells in eight logic blocks • 128 I/O pins Functional Description

Contextual Info: CY7C375i UltraLogic 128-Macrocell Flash CPLD Features Functional Description • • • • 128 macrocells in eight logic blocks 128 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogrammable ISR™ Flash technology — JTAG Interface

208-Lead

Abstract: CY37512 CY37512V CY37512VP208-66NI ultraISR CABLE
Contextual Info: PRELIMINARY CY37512V UltraLogic 3.3V 512-Macrocell ISR™ CPLD — tPD = 15 ns Features • 512 macrocells in 32 logic blocks • 3.3V In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

CY37256P160-125UMB

Abstract: CY37256P160-83UMB CY37256 CY37256V CY37256-125 CY37256P160-125AI
Contextual Info: PRELIMINARY CY37256 UltraLogic 256-Macrocell ISR™ CPLD Features • • • • • • • • • • 256 macrocells in sixteen logic blocks • In-System Reprogrammable ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

Contextual Info: 75i CY7C375i UltraLogic 128-Macrocell Flash CPLD Features Functional Description • • • • 128 macrocells in eight logic blocks 128 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogrammable ISR™ Flash technology — JTAG Interface

Contextual Info: CY7C375i UltraLogic 128-Macrocell Flash CPLD Features Functional Description • • • • 128 macrocells in eight logic blocks 128 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogrammable ISR™ Flash technology — JTAG Interface

Contextual Info: CY7C375i UltraLogic 128-Macrocell Flash CPLD Features • 3.3V or 5.0V I/O operation • Available in 160-pin TQFP, CQFP, and PGA packages • 128 macrocells in eight logic blocks • 128 I/O pins Functional Description • Five dedicated inputs including 4 clock pins

Contextual Info: CY37192V UltraLogic 3.3V 192-Macrocell ISR™ CPLD — tPD = 12.0 ns Features — tS = 7.0 ns • 192 macrocells in twelve logic blocks • IEEE standard 3.3V operation — 3.3V ISR • • • • • • • • • — 5V tolerant • 3.3V In-System Reprogrammable™ ISR™

CY37192

Abstract: CY37192V
Contextual Info: PRELIMINARY CY37192V UltraLogic 3.3V 192-Macrocell ISR™ CPLD — tPD = 12 ns Features — tS = 7 ns • 192 macrocells in twelve logic blocks • IEEE standard 3.3V operation — 3.3V ISR • • • • • • • • • — 5V tolerant • 3.3V In-System Reprogrammable™ ISR™

CY37192

Abstract: CY37192V
Contextual Info: Back PRELIMINARY CY37192V UltraLogic 3.3V 192-Macrocell ISR™ CPLD — tPD = 12 ns Features — tS = 7 ns • 192 macrocells in twelve logic blocks • IEEE standard 3.3V operation — 3.3V ISR • • • • • • • • • — 5V tolerant • 3.3V In-System Reprogrammable™ ISR™

CY37192

Abstract: CY37192V tlp 453
Contextual Info: PRELIMINARY CY37192 UltraLogic 192-Macrocell ISR™ CPLD Features • • • • • • • • • • • 192 macrocells in twelve logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

Contextual Info: CY37192 UltraLogic 192-Macrocell ISR™ CPLD • • • • • • • • • • Features • 192 macrocells in twelve logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

CY37512

Abstract: CY37512V AE O47 CY37512P208-83UMB
Contextual Info: Back PRELIMINARY CY37512 UltraLogic 512-Macrocell ISR™ CPLD Features • 512 macrocells in 32 logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes — Design changes don’t cause timing changes