O118 Search Results

7555-T

Abstract: M1FM3
Contextual Info: Al t hough we ar e cons t ant l ymak i ng ev er yef f or tt oi mpr ov et he qual i t yand r el i abi l i t yofourpr oduct s ,t her enev er t hel es sr emai nsacer t ai npr obabi l i t yt hatt he s emi conduct orpr oduct smayoccas i onal l yf ai lormal f unct

CY37384

Abstract: CY37384V
Contextual Info: PRELIMINARY CY37384 UltraLogic 384-Macrocell ISR™ CPLD — tS = 5.5 ns Features • 384 macrocells in 24 logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming • • • • • • • • • • — Design changes don’t cause pinout changes

Contextual Info: S E M I C O N D U C T O R Revised April 1999 TM 74LCX16652 Low Voltage Transceiver/Register with 5V Tolerant Inputs and Outputs General Description Features T h e LCX16652 contains sixteen non-inverting bidirectional bus transceivers with 3-STATE outputs providing m ulti­

Contextual Info: S E M I C O N D U C T O R August 1998 Revised April 1999 TM 74LCXR162245 Low Voltage 16-Bit Bidirectional Transceiver with 5V Tolerant Inputs/Outputs and 26£1 Series Resistors in the Outputs General Description Features T h e LCXR 162245 contains sixteen non-inverting bidirec­

Contextual Info: S E M I C O N D U C T O R Revised November 1998 TM 74ACTQ16240 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs General Description Features The ACTQ16240 contains sixteen inverting buffers with 3STATE outputs designed to be employed as a memory and

a5gnd

Abstract: A1 GNC
Contextual Info: °c to b e H r1 A989 . 1 Revised A ugust 1999 74FR16541 16-Bit Buffer/Line Driver with 3-STATE Outputs General Description Features T h e 74FR16541 contains sixteen non-inverting buffers with 3-STATE outputs designed to be em ployed as a m em ory and address driver, clock driver, o r bus-oriented tra n sm it­

Contextual Info: A I R C H I L D pe b m 7 J 9 Revised Aprii 1999 S E M ¡CONDUCTOR TM General Description Features T h e LC X16374 contains sixteen non-inverting D -type flipflops w ith 3-STATE outputs and is intended fo r bus oriented applications. The device is byte controlled. A buffered clock

d4184

Abstract: transistor N14 193 atmel application note AT6002 AT6003 AT6005 AT6010
Contextual Info: Features • High-performance • • • • • • • • • – System Speeds > 100 MHz – Flip-flop Toggle Rates > 250 MHz – 1.2 ns/1.5 ns Input Delay – 3.0 ns/6.0 ns Output Delay Up to 204 User I/Os Thousands of Registers Cache Logic Design

65x2

Abstract: SED1530DAA SED1530T SED1530 SED1530D0 SED1530DA SED1530DF SED1531 SED1531D0 SED1532
Contextual Info: PF777-03 Series SED1530SED1530 Series Dot Matrix LCD Controller Driver SSC5000Series ● Ultra Low Power Consumption ● Built-in Power Supply Circuit for LCD ● 133 Driver Output • DESCRIPTION The SED1530 series is a single-chip LCD driver for dot-matrix liquid crystal displays LCD’s which is directly

Contextual Info: ! ^ jjjjjy '•ttttttttWÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄW1- JM N K t t ♦ < ij / 5; PRELIMINARY *^ ' CY37384 UltraLogic 384-Macrocell ISR™ CPLD — ts = 5.5 ns Features — tco = 6 ns • 384 macrocells in 24 logic blocks • In-System Reprogrammable™ (ISR™

Contextual Info: S E M I C O N D U C T O R Revised April 1999 TM 74LCX16501 18-Bit Universal Bus Transceivers with 5V Tolerant Inputs and Outputs General Description Features The LCX16501 is an 18-bit universal bus transceiver com ­ bining D-type latches and D-type flip-flops to a llow data

Contextual Info: UPD43256BGX-B12-EJA 1/2 IL16 ∗∗∗∗∗ C-MOS 256k (32kx8) BIT STATIC RAM –TOP VIEW– OE A11 A9 A8 A13 WE A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NC NC VDD (+2.7 to 5.5V) GND NC A0-14 ; ADDRESS INPUTS I/O1-18 ; DATA INPUTS/OUTPUTS

3M-2520-6002-UG

Abstract: TNETX3100 HF70ACB453215T MAX232ACSE 4Mbit eeprom DIAMONDBACK TNETX4090 TNETX3110 TNETX3150 "Spanning Tree"
Contextual Info: Diamondback Management Card Schematic Description and Schematics APPLICATION REPORT: SPWA033 World Wide Broadband Access Group LAN Products May 1999 IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice, and advise

K 3673

Abstract: 3673 SN 46 LS 46 LC4103 LC4103C LC4103TAB-01 LC4103TAB-02
Contextual Info: * Ordering number:ENN 5193B CMOS P-sub LC4103TAB-01, 4103TAB-02, 4103C STN LCD Dot Matrix Common Driver Preliminary Overview The LC4103 is a common driver IC for large-scale dot matrix LCD displays, It includes a 160-bit bidirectional shift register and 4-level LCD drivers. The number of bits can

ic 4040

Abstract: 4040 cmos ci 4040 cmos 4040 stv 4325 O129-O135 PD16707 4040
Contextual Info: お客様各位 カタログ等資料中の旧社名の扱いについて 2010 年 4 月 1 日を以って NEC エレクトロニクス株式会社及び株式会社ルネサステクノロジ が合併し両社の全ての事業が当社に承継されております。従いまして、本資料中には旧社

45937

Abstract: 45580 sis 648 data 7457 frequency divider SiS chipset 486 7815 2A PCI 6602 sdr 20000 sis 6205 ICS952011
Contextual Info: ICS952011 Integrated Circuit Systems, Inc. Programmable Timing Control Hub for P4™ processor Recommended Application: SIS 645/645DX/648/650 style chipsets. Output Features: • 2 - Pairs of differential CPUCLKs differential current mode • 1 - SDRAM @ 3.3V

Contextual Info: R e v is e d J a n u a ry 199 9 EMICQNDUCTGR tm 74 ABT162244 16-Bit Buffer/Line Driver with 25Q Series Resistors in the Outputs General Description Features T h e A B T 1 6 2 2 4 4 c o n ta in s s ix te e n n o n -in v e rtin g b u ffe rs w ith • S e p a ra te c o n tro l lo g ic fo r e a c h n ib b le

O16I

Abstract: 7256P 99L0
Contextual Info: PREUM INAm Ultra37256 UltraLogic 256-Macrocell ISR™ CPLD — tco = 4.5 ns Features Product-term clocking IEEE1149.1 JTAG boundary scan Programmable slew rate control on individual l/Os Low power option on individual logic block basis 5V and 3.3V I/O capability

2A299

Abstract: HP3070 MArking 3A5 AMD CPLD Mach 1 to 5 MACH5-256
Contextual Info: MACH 5 FAMILY 1 FINAL COM’L: -7/10/12/15 IND: -10/12/15/20 MACH5-256 MACH5-256/68-7/10/12/15 MACH5-256/120-7/10/12/15 MACH5-256/104-7/10/12/15 MACH5-256/160-7/10/12/15 Fifth Generation MACH Architecture DISTINCTIVE CHARACTERISTICS ◆ Fifth generation MACH architecture

MACH4 cpld amd

Abstract: mach 1 family amd HP3070
Contextual Info: MACH 4 FAMILY 1 MACH 4 Family High Performance EE CMOS Programmable Logic With Maximum Ease Of Use DISTINCTIVE CHARACTERISTICS ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ MACH 4 Family ◆ High-performance, EE CMOS CPLD family SpeedLocking for guaranteed fixed timing -7/10/12/15 ns tPD

marking 3B3

Abstract: 32V16 mach 1 family amd 3A10 MC5C1 MACH5 cpld amd
Contextual Info: PRELIMINARY COM’L: -7/10/12/15 IND: -10/12/15/20 The MACH5-256 MACH5-256/68-7/10/12/15/20 MACH5-256/104-7/10/12/15/20 MACH5-256/120-7/10/12/15/20 MACH5-256/160-7/10/12/15/20 Fifth Generation MACH Architecture DISTINCTIVE CHARACTERISTICS • Fifth generation MACH architecture

Contextual Info: 1 MACH 5 FAMILY MACH 5 Family Fifth Generation MACH Architecture DISTINCTIVE CHARACTERISTICS ◆ ◆ ◆ ◆ ◆ ◆ ◆ Publication# 20446 Amendment/0 Rev: D Issue Date: August 1997 MACH 5 Family ◆ Fifth generation MACH architecture — 100% routable

MACH111SP

Abstract: MACH465 MACH4-256 mach4256
Contextual Info: MACH 4 FAMILY 1 FINAL COM’L: -10/12/15 IND:-12/14/18 MACH4-256/MACH4LV-256 High-Performance EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ 208 pins in PQFP 256 macrocells 10 ns tPD Commercial, 12 ns tPD Industrial

MC189

Abstract: 9300 4b10 2D15 marking 1A15 HP 3D6 1b61a0 MACH5-320 ae 4b15
Contextual Info: MACH 5 FAMILY 1 FINAL COM’L:-7/10/12/15 IND:-10/12/15/20 MACH5-320/MACH5LV-320 MACH5-320/120-7/10/12/15 MACH5-320/192-7/10/12/15 MACH5LV-320/184-7/10/12/15 MACH5-320/160-7/10/12/15 MACH5LV-320/120-7/10/12/15 MACH5LV-320/192-7/10/12/15 MACH5-320/184-7/10/12/15