OAI22 CAPACITANCE Search Results

OAI22 CAPACITANCE Result Highlights (5)

Part	Manufacturer	Description
GC331AD7LP333KX18J	Murata Manufacturing Co Ltd	High Effective Capacitance & High Ripple Current Chip Multilayer Ceramic Capacitors for Automotive
GC331BD7LQ333KX18K	Murata Manufacturing Co Ltd	High Effective Capacitance & High Ripple Current Chip Multilayer Ceramic Capacitors for Automotive
GC332DD7LQ683KX18K	Murata Manufacturing Co Ltd	High Effective Capacitance & High Ripple Current Chip Multilayer Ceramic Capacitors for Automotive
GC355DD7LP474KX18K	Murata Manufacturing Co Ltd	High Effective Capacitance & High Ripple Current Chip Multilayer Ceramic Capacitors for Automotive
GC355XD7LQ564KX17L	Murata Manufacturing Co Ltd	High Effective Capacitance & High Ripple Current Chip Multilayer Ceramic Capacitors for Automotive

OAI22 CAPACITANCE Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
fan 7320 Abstract: atmel 936 ttl buffer MG2014P MG2044P MG2142P MG2270P TM1019 radiation hard PLL OAI22 capacitance Contextual Info: MG2RTP Radiation Hardened 0.5 Micron Sea of Gates Introduction The MG2RTP series is a 0.5 micron, array based, CMOS product family. Several arrays up to 490k cells cover all system integration needs. The MG2RTP is manufactured using SCMOS3/2RTP, a 0.5 micron drawn, 3 metal	Original	OAI22 fan 7320 atmel 936 ttl buffer MG2014P MG2044P MG2142P MG2270P TM1019 radiation hard PLL OAI22 capacitance	PDF
fan 7320 Abstract: LA 4440 circuit diagram atmel 936 MG2014P MG2044P MG2142P TM1019 0.5-um CMOS standard cell library 4116G Contextual Info: Features • • • • • • • • • • • • • • • • • • • • • • • • • Full Range of Matrices up to 490K Cells Utilization Ratio Allows Considering a Design Complexity up to 350K Gates 0.5 µm Drawn CMOS, 3 Metal Layers, Sea of Gates	Original	4116G fan 7320 LA 4440 circuit diagram atmel 936 MG2014P MG2044P MG2142P TM1019 0.5-um CMOS standard cell library	PDF
star delta wiring diagram with timer Abstract: atmel 422 ATMEL 634 atmel 946 star delta connection circuit diagrams star delta wiring diagram synopsys Platform Architect DataSheet ttl buffer MG2044E MG2091E Contextual Info: Features • • • • • • • • • • • • • • • • • • • • • • • • Full Range of Matrices with up to 480K Available Gates 0.5 µm Drawn CMOS, 3 Metal Layers, Sea of Gates RAM and DPRAM Compilers Library Optimized for Synthesis, Floor Plan and Automatic Test Generation ATG	Original	4115H star delta wiring diagram with timer atmel 422 ATMEL 634 atmel 946 star delta connection circuit diagrams star delta wiring diagram synopsys Platform Architect DataSheet ttl buffer MG2044E MG2091E	PDF
atmel 946 Abstract: X-TAL 20m atmel 422 AtMEL 624 ATMEL 634 OAI22 MG2044E MG2091E MG2140E MG2194E Contextual Info: Features • • • • • • • • • • • • • • • • • • • • • • • Full Range of Matrices up to 700K Cells 0.5 µm Drawn CMOS, 3 Metal Layers, Sea of Gates RAM and DPRAM Compilers Library Optimized for Synthesis, Floor Plan and Automatic Test Generation ATG	Original	4115G atmel 946 X-TAL 20m atmel 422 AtMEL 624 ATMEL 634 OAI22 MG2044E MG2091E MG2140E MG2194E	PDF
MG2RTP Abstract: MG2044P MG2142P MG2270P aero MS 3475 4116K Contextual Info: Features • • • • • • • • • • • • • • • • • • • • • • • • • Full Range of Matrices up to 270K Available Gates 0.5 µm Drawn CMOS, 3 Metal Layers, Sea of Gates RAM and DPRAM Compilers Library Optimized for Synthesis, Floor Plan and Automatic Test Generation ATG	Original	4116K MG2RTP MG2044P MG2142P MG2270P aero MS 3475	PDF
ATMEL 634 Abstract: 4115I MG2044E MG2091E MG2194E MG2265E MG2360E 0.5-um CMOS standard cell library Contextual Info: Features • • • • • • • • • • • • • • • • • • • • • • • • • Full Range of Matrices with up to 480K Available Gates 0.5 µm Drawn CMOS, 3 Metal Layers, Sea of Gates RAM and DPRAM Compilers Library Optimized for Synthesis, Floor Plan and Automatic Test Generation ATG	Original	4115I ATMEL 634 MG2044E MG2091E MG2194E MG2265E MG2360E 0.5-um CMOS standard cell library	PDF
MG2044P Abstract: MG2142P MG2270P 0.5-um CMOS standard cell library Contextual Info: Features • • • • • • • • • • • • • • • • • • • • • • • • • Full Range of Matrices up to 270K Available Gates 0.5 µm Drawn CMOS, 3 Metal Layers, Sea of Gates RAM and DPRAM Compilers Library Optimized for Synthesis, Floor Plan and Automatic Test Generation ATG	Original	4116I MG2044P MG2142P MG2270P 0.5-um CMOS standard cell library	PDF
32M DPRAM Abstract: MG2044E MG2091E MG2140E MG2194E MG2265E MG2360E MG2480E MG2700E TM1019 Contextual Info: MG2RT Radiation Tolerant 0.5 Micron Sea of Gates Introduction The MG2RT series is a 0.5 micron, array based, CMOS product family. Several arrays up to 700k cells cover all system integration needs. The MG2RT is manufactured using SCMOS3/2RT, a 0.5 micron drawn, 3 metal layers	Original	Tree65 32M DPRAM MG2044E MG2091E MG2140E MG2194E MG2265E MG2360E MG2480E MG2700E TM1019	PDF
X-TAL 20m Contextual Info: Features • • • • • • • • • • • • • • • • • • • • • • • Full Range of Matrices up to700K Cells 0.5 µm Drawn CMOS, 3 Metal Layers, Sea of Gates RAM and DPRAM Compilers Library Optimised for Synthesis, Floor Plan & Automatic Test Generation ATG	Original	to700K X-TAL 20m	PDF
atmel 936 Abstract: transistor SMD DK synopsys Platform Architect DataSheet MG2044P MG2142P TM1019 0.5-um CMOS standard cell library Atmel 440 Contextual Info: Features • • • • • • • • • • • • • • • • • • • • • • • • • Full Range of Matrices up to 270K Available Gates 0.5 µm Drawn CMOS, 3 Metal Layers, Sea of Gates RAM and DPRAM Compilers Library Optimized for Synthesis, Floor Plan and Automatic Test Generation ATG	Original	4116H atmel 936 transistor SMD DK synopsys Platform Architect DataSheet MG2044P MG2142P TM1019 0.5-um CMOS standard cell library Atmel 440	PDF
AtMEL 624 Abstract: XTAL SMD Packages atmel 946 0.5-um CMOS standard cell library atmel 044 Contextual Info: Features • • • • • • • • • • • • • • • • • • • • • • • • • Full Range of Matrices with up to 480K Available Gates 0.5 µm Drawn CMOS, 3 Metal Layers, Sea of Gates RAM and DPRAM Compilers Library Optimized for Synthesis, Floor Plan and Automatic Test Generation ATG	Original	4115J AtMEL 624 XTAL SMD Packages atmel 946 0.5-um CMOS standard cell library atmel 044	PDF
fan 7320 Abstract: atmel 936 ttl buffer UART using VHDL MG2014P MG2044P MG2142P MG2270P TM1019 Contextual Info: Features • • • • • • • • • • • • • • • • • • • • • • • • Full Range of Matrices up to 490k Cells 0.5 µm Drawn CMOS, 3 Metal Layers, Sea of Gates RAM and DPRAM Compilers Library Optimised for Synthesis, Floor Plan & Automatic Test Generation ATG	Original	484full fan 7320 atmel 936 ttl buffer UART using VHDL MG2014P MG2044P MG2142P MG2270P TM1019	PDF
atmel 424 Abstract: AMBIT inverter atmel 545 ATMEL 340 crystal oscillator buffer Structure of D flip-flop DFFSR s051 crystal OAI222 CMOS Transmission gate Specifications Tri-State Buffer CMOS Contextual Info: Features • 0.5 µm Drawn Gate Length 0.45µm Leff Sea-of-Gates Architecture With Triple Level Metal • 3.3V Operation • 5.0V Compatible Input Buffers • On-chip Phase Locked Loop (PLL) Available to Synthesize Frequencies up to 150 MHz • • • •	Original	ATL50 0753B 11/99/xM atmel 424 AMBIT inverter atmel 545 ATMEL 340 crystal oscillator buffer Structure of D flip-flop DFFSR s051 crystal OAI222 CMOS Transmission gate Specifications Tri-State Buffer CMOS	PDF
Structure of D flip-flop DFFSR Abstract: AOI222 INV4 OAI23 atmel 424 MUX CMOS 0753B 5-input NAND Gates pic single phase inverter OAI22 Contextual Info: ATL50 Features • • • • • • • • 0.5µm Drawn Gate Length 0.45µm Leff Sea-of-Gates Architecture With Triple Level Metal 3.3 Volt Operation 5.0 Volt compatible input buffers On-Chip Phase Locked Loop (PLL) Available to Synthesize Frequencies up to	Original	ATL50 ATL50 Structure of D flip-flop DFFSR AOI222 INV4 OAI23 atmel 424 MUX CMOS 0753B 5-input NAND Gates pic single phase inverter OAI22	PDF

atmel 0726 Abstract: OAI22 0.5-um CMOS standard cell library Contextual Info: Marcom Nantes Technical Document Release Document Identification ✔ Datasheet Application note Manual Errata Sheet Lit.# / Rev.letter Doc. Date 4116J 10/20/2004 Other technical Part Number Product Description MG2RTP Rad Hard 190K Used Gates 0.5 µm CMOS Sea of Gates	Original	4116J atmel 0726 OAI22 0.5-um CMOS standard cell library	PDF
MG2265E Abstract: MG2360E MG2044E MG2091E MG2194E ATMEL 634 atmel 946 Contextual Info: Features • • • • • • • • • • • • • • • • • • • • • • • • • Full Range of Matrices with up to 480K Available Gates 0.5 µm Drawn CMOS, 3 Metal Layers, Sea of Gates RAM and DPRAM Compilers Library Optimized for Synthesis, Floor Plan and Automatic Test Generation ATG	Original	4115K MG2265E MG2360E MG2044E MG2091E MG2194E ATMEL 634 atmel 946	PDF
ut161 Abstract: bip 373 UT162 AOI13 UT163 half adder circuit using 2*1 multiplexer G/transistor bip 109 UT169 SCA92 AOI21 Contextual Info: Radiation-Hardened Semicustom Products UTD-R Gate Array Family Data Sheet UNITED TECHNOLOGIES MICROELECTRONICS CENTER April 1990 FEA TU RES □ Total dose 1 x 106 rads Si to this data sheet specification according to M IL-STD-883, M ethod 1019 □ Total dose 1 x 107 rads (Si) functional	OCR Scan	IL-STD-883, cobalt-60 150mA 500msec -3-4-90-PD ut161 bip 373 UT162 AOI13 UT163 half adder circuit using 2*1 multiplexer G/transistor bip 109 UT169 SCA92 AOI21	PDF
AOI222 Abstract: P02B OAI222 Contextual Info: ATL50 Features • • • • • • • • 0.5\|.im Drawn Gate Length 0.45\|am Left Sea-of-Gates Architecture With Triple Level Metal 3.3 Volt Operation 5.0 Volt compatible input buffers On-Chip Phase Locked Loop (PLL) Available to Synthesize Frequencies up to	OCR Scan	ATL50 ATL50 AOI222 P02B OAI222	PDF
MQFPL160 Contextual Info: T em ic MG2RT Semiconductors Radiation Tolerant 0.5-jiim CMOS Sea-of-Gates 100k Rad Low Dose Rate Introduction The MG2RT series is a 0.5 micron, array based, CMOS product family. Several arrays up to 700k cells cover all system integration needs. The MG2RT is manufactured	OCR Scan	OAI22 MQFPL160	PDF
3 to 8 bit decoder vhdl IEEE format Abstract: ATL60 ATLS60 PO61 ttl buffer Contextual Info: ATL60 Features x x x x x x x x 0.6Pm Drawn Gate Length 0.5Pm Leff Sea-of-Gates Architecture With Triple Level Metal 5.0 Volt, 3.3 Volt, and 2.0 Volt Operation Including Mixed Voltages On Chip Phase Locked Loop Available to Synthesize Frequencies up to 150 MHz and Manage Chip-to-Chip Clock Skew	Original	ATL60 ATL60 3 to 8 bit decoder vhdl IEEE format ATLS60 PO61 ttl buffer	PDF
TTL Schmitt-Trigger Inverters Abstract: Structure of D flip-flop DFFSR Tri-State Buffer CMOS TTL 3 input or gate ttl buffer TTL nand 3 input or gate 3 input Decoders actel PLL schematic AOI222 Contextual Info: ATL60 Features • • • • • • • • 0.6µm Drawn Gate Length 0.5µm Leff Sea-of-Gates Architecture With Triple Level Metal 5.0 Volt, 3.3 Volt, and 2.0 Volt Operation Including Mixed Voltages On Chip Phase Locked Loop Available to Synthesize Frequencies up to	Original	ATL60 ATL60 TTL Schmitt-Trigger Inverters Structure of D flip-flop DFFSR Tri-State Buffer CMOS TTL 3 input or gate ttl buffer TTL nand 3 input or gate 3 input Decoders actel PLL schematic AOI222	PDF
Tri-State Buffer CMOS Abstract: PTS41 books schmitt trigger cmos buffer 8x buffer cmos ATL60 ATLS60 mux8n AOI222 Contextual Info: ATL60 Features • • • • • • • • 0.6µm Drawn Gate Length 0.5µm Leff Sea-of-Gates Architecture With Triple Level Metal 5.0 Volt, 3.3 Volt, and 2.0 Volt Operation Including Mixed Voltages On Chip Phase Locked Loop Available to Synthesize Frequencies up to	Original	ATL60 ATL60 Tri-State Buffer CMOS PTS41 books schmitt trigger cmos buffer 8x buffer cmos ATLS60 mux8n AOI222	PDF
PO61 Abstract: ATMEL 340 atmel 424 ATLS60 ATL60 ttl buffer 3.6v Tri-State Buffer bga ambit inverter circuit AOI222 ATMEL 218 Contextual Info: Features • • • • • • • • 0.6 µm Drawn Gate Length 0.5 µm Leff Sea-of-Gates Architecture with Triple Level Metal 5.0V, 3.3V and 2.0V Operation including Mixed Voltages On-chip Phase Locked Loop Available to Synthesize Frequencies up to 150 MHz and	Original	ATL60 0388C 11/99/xM PO61 ATMEL 340 atmel 424 ATLS60 ttl buffer 3.6v Tri-State Buffer bga ambit inverter circuit AOI222 ATMEL 218	PDF
atmel 952 Abstract: atmel h 952 ATL35 vhdl code for flip-flop jk flip flop to d flip flop conversion RTL 204 605 vhdl code for D Flipflop dssb oak dsp AOI222 Contextual Info: Features • High Speed - 150 ps Gate Delay - 2 input NAND, FO=2 nominal • Up to 3.7 Million Used Gates and 976 Pins • System Level Integration Technology ™ ARM7TDMI and AVR RISC Microcontrollers, OakDSP™ and Lode™DSP Cores, 10T/100 Ethernet MAC, USB and PCI Cores,	Original	10T/100 ATL35 atmel 952 atmel h 952 vhdl code for flip-flop jk flip flop to d flip flop conversion RTL 204 605 vhdl code for D Flipflop dssb oak dsp AOI222	PDF

OAI22 CAPACITANCE Search Results

OAI22 CAPACITANCE Result Highlights (5)

OAI22 CAPACITANCE Datasheets Context Search

fan 7320

fan 7320

star delta wiring diagram with timer

atmel 946

MG2RTP

ATMEL 634

MG2044P

32M DPRAM

X-TAL 20m

atmel 936

AtMEL 624

fan 7320

atmel 424

Structure of D flip-flop DFFSR

atmel 0726

MG2265E

ut161

AOI222

MQFPL160

3 to 8 bit decoder vhdl IEEE format

TTL Schmitt-Trigger Inverters

Tri-State Buffer CMOS

PO61

atmel 952