OC3 TUBE Search Results

Contextual Info: INTEGRATED CIRCUITS DATA SHEET TZA3033 SDH/SONET STM1/OC3 transimpedance amplifier Objective specification File under Integrated Circuits, IC19 1998 Jul 08 Philips Semiconductors Objective specification SDH/SONET STM1/OC3 transimpedance amplifier TZA3033 FEATURES

TZA3034TD

Abstract: TZA3034TD-T
Contextual Info: INTEGRATED CIRCUITS DATA SHEET TZA3034 SDH/SONET STM1/OC3 postamplifier Product specification Supersedes data of 1999 Mar 16 File under Integrated Circuits, IC19 1999 Nov 03 Philips Semiconductors Product specification SDH/SONET STM1/OC3 postamplifier TZA3034

GR-1244-CORE

Abstract: MT9045 MT9045AN MT9045AN1 MT9045ANR TR62411 74HC14 application oscillator 20mhz
Contextual Info: MT9045 T1/E1/OC3 System Synchronizer Data Sheet Features • February 2005 Supports AT&T TR62411 and Bellcore GR-1244CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces Ordering Information MT9045AN 48 Pin SSOP MT9045ANR 48 Pin SSOP

Contextual Info: MK2049-36 3.3 Volt Communications Clock PLL Description Features The MK2049-36 is a Phased Locked Loop PLL based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-36 generates T1, E1, T3, E3, OC3 and

Contextual Info: MK2049-36 3.3 Volt Communications Clock PLL Description Features The MK2049-36 is a Phased Locked Loop PLL based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-36 generates T1, E1, T3, E3, OC3 and

siemens Logo 230 rc manual

Contextual Info: MT9044 T1/E1/OC3 System Synchronizer Data Sheet Features • November 2004 Supports AT&T TR62411 and Bellcore GR-1244CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces • Supports ITU-T G.813 Option 1 clocks for 2048 kbit/s interfaces

MAN05

Abstract: MK2049-34 MK2049-36 MK2049-36SI MK2049-45 TR62411 ETS300 GR-1244
Contextual Info: DATASHEET MK2049-36 3.3 VOLT COMMUNICATIONS CLOCK PLL Description Features The MK2049-36 is a Phased Locked Loop PLL based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-36 generates T1, E1, T3, E3, OC3 and other communications

ETS300

Abstract: GR-1244 MAN05 MK2049-34 MK2049-36 MK2049-45 TR62411
Contextual Info: DATASHEET MK2049-36 3.3 VOLT COMMUNICATIONS CLOCK PLL Description Features The MK2049-36 is a Phased Locked Loop PLL based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-36 generates T1, E1, T3, E3, OC3 and other communications

Contextual Info: MK2049-36 3.3V Communications Clock PLL Description Features The MK2049-36 is a Phased Locked Loop PLL based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-36 generates T1, E1, T3, E3, OC3 and

Contextual Info: MK2049-36 3.3V Communications Clock PLL Description Features The MK2049-36 is a Phased Locked Loop PLL based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-36 generates T1, E1, T3, E3, OC3 and

100BASE-LX10

Abstract: GR-468
Contextual Info: Fast Ethernet SFP Transceiver SP-FE-LX Features • Compliant with OC3/STM-1, IEEE 802.3ah, 100BASE-LX10 • Single 3.3 V Supply • 10 dB Minimum Link Budget • 15 km Minimum Reach • 1310nm FP Laser • Commercial Temperature Available -Cxx • Industrial Temperature Available (-Txx)

ETS300

Abstract: GR-1244 MAN05 MK2049-34 MK2049-36 MK2049-36SI MK2049-36SITR MK2049-45 TR62411 MK2049-36SILF
Contextual Info: DATASHEET MK2049-36 3.3 VOLT COMMUNICATIONS CLOCK PLL Description Features The MK2049-36 is a Phased Locked Loop PLL based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-36 generates T1, E1, T3, E3, OC3 and other communications

ETS300

Abstract: GR-1244 MAN05 MK2049-34 MK2049-36 MK2049-45 TR62411
Contextual Info: DATASHEET MK2049-36 3.3 VOLT COMMUNICATIONS CLOCK PLL Description Features The MK2049-36 is a Phased Locked Loop PLL based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-36 generates T1, E1, T3, E3, OC3 and other communications

siemens Logo 230 rc manual

Abstract: schmit GTO MODULE GR-1244-CORE MT9044 MT9044AL MT9044AL1 MT9044AP MT9044AP1 MT9044APR
Contextual Info: MT9044 T1/E1/OC3 System Synchronizer Data Sheet Features • November 2005 Supports AT&T TR62411 and Bellcore GR-1244CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces • Supports ITU-T G.813 Option 1 clocks for 2048 kbit/s interfaces

ICS894D115I-01

Abstract: tube OC3 ICS894D115BGI-01 ICS894D115I-04 ICS894D115I vsc8115 OC3 Tube
Contextual Info: ICS894D115I-01 OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE General Description Features The ICS894D115I-01 is a clock and data recovery circuit. The device is designed to extract the clock HiPerClockS signal from a NRZ-coded STM-4 OC-12/STS-12 or

Contextual Info: ICS894D115I-01 OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE General Description Features The ICS894D115I-01 is a clock and data recovery circuit. The device is designed to extract the clock HiPerClockS signal from a NRZ-coded STM-4 OC-12/STS-12 or

ICS894D115I-04

Abstract: led clock circuit diagram ICS894D115I-01 ICS894D115AGI-04 ICS894D115I
Contextual Info: ICS894D115I-04 OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE General Description Features The ICS894D115I-04 is a clock and data recovery circuit. The device is designed to extract the clock HiPerClockS signal from a NRZ-coded STM-4 OC-12/STS-12 or

Contextual Info: ICS894D115I-04 OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE General Description Features The ICS894D115I-04 is a clock and data recovery circuit. The device is designed to extract the clock HiPerClockS signal from a NRZ-coded STM-4 OC-12/STS-12 or

OC3 Tube

Abstract: od3 tube od3 Voltage Regulator ob3 tube tube OC3 0C3 TUBE gas filled voltage regulator ST-12 90 VOLTS REGULATOR Scans-0017246
Contextual Info: a:\ m y S Y L V A N IA 0B3 engineering data service 0C3, 0D3 MECHANICAL DATA B u l b . ST-12 B a s e . B6-3, Small Shell Octal, 6-Pin

OC3 Tube

Abstract: C813C Nippon capacitors
Contextual Info: PRELIMINARY ICS894D115I-01 OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE General Description Features The ICS894D115I-01 is a clock and data recovery circuit. The device is designed to extract the clock HiPerClockS signal from a NRZ-coded STM-4 OC-12/STS-12 or

OC3 Tube

Abstract: tube OC3 SP-03-MX
Contextual Info: OC-3 SFP Transceiver SP-03-MX Features • Data Rate 155.52 Mb/s • Single 3.3V Supply • 2 km Reach for 62.5/125 mm MMF 500 MHz•km • 1310nm FP Laser • SFP MSA SFF-8074i Compliant • Compliant with GR-253 OC-3 SR1 • Telcordia GR-468 Compliant

lucent OC12 receiver

Contextual Info: Data Sheet September 1998 group y' Lucent Technologies Bell Labs Innovations 1345-Type Receiver with Clock Recovery and Data Retiming Applications • Telecommunications — Inter- and intraoffice SONET/ITU-T SDH — Subscriber loop — Metropolitan area networks

EIA-625

Abstract: ecl 10K signetics LUCENT InGaAs 1345FMPC GR-253-CORE TR-NWT-000468 pin optical fiber lucent DS99-073LWP
Contextual Info: Data Sheet January 2000 1345-Type Receiver with Clock Recovery and Data Retiming Applications • Telecommunications — Inter- and intraoffice SONET/ITU-T SDH — Subscriber loop — Metropolitan area networks ■ High-speed data communications Description

lucent OC12 receiver

Abstract: Lucent receiver GR-253-CORE TR-NWT-000468 8833 signetics 1345cnpc
Contextual Info: Data Sheet January 1999 1345-Type Receiver with Clock Recovery and Data Retiming Applications • Telecommunications — Inter- and intraoffice SONET/ITU-T SDH — Subscriber loop — Metropolitan area networks ■ High-speed data communications Description